JAJSKT9A December   2020  – June 2021 PCMD3140

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 6.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 6.10 Timing Requirements: PDM Digital Microphone Interface
    11. 6.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 6.12 Timing Diagrams
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 7.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 7.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 7.3.7 Voice Activity Detection (VAD)
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Page 0 Registers
      2. 7.6.2 Page 1 Registers
      3. 7.6.3 Programmable Coefficient Registers
        1. 7.6.3.1 Programmable Coefficient Registers: Page 2
        2. 7.6.3.2 Programmable Coefficient Registers: Page 3
        3. 7.6.3.3 Programmable Coefficient Registers: Page 4
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Four-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PERFORMANCE FOR PDM INPUT CONVERSION
SNR Signal-to-noise ratio, A-weighted(1) (2) (3) No signal, input generated using 5th-order PDM modulator  130 dB
No signal, input generated using 4th-order PDM modulator  118
DR Dynamic range, A-weighted(2) (3) –60-dB full-scale signal input, input generated using 5th-order PDM modulator  127 dB
–60-dB full-scale signal input, input generated using 4th-order PDM modulator  116
OTHER PARAMETERS
Digital volume control range Programmable 0.5-dB steps –100 27 dB
Output data sample rate Programmable 7.35 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 12 Hz
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS 2.1 µVRMS
MICBIAS voltage MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF V
MICBIAS voltage MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF × 1.096 V
MICBIAS voltage Bypass to AVDD with 5-mA load AVDD – 0.2 V
MICBIAS current drive 5 mA
MICBIAS load regulation MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load 0 0.6 1 %
MICBIAS overcurrent protection threshold 6.1 mA
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except PDMCLK_GPO1, SDA and SCL,
IOL = –2 mA, IOVDD 1.8-V operation		 0.45 V
All digital pins except PDMCLK_GPO1, SDA and SCL,
IOL = –2 mA, IOVDD 3.3-V operation		 0.4
VOH High-level digital output voltage All digital pins except PDMCLK_GPO1, SDA and SCL,
IOH = 2 mA, IOVDD 1.8-V operation		 IOVDD – 0.45 V
All digital pins except PDMCLK_GPO1, SDA and SCL,
IOH = 2 mA, IOVDD 3.3-V operation		 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 x IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 x IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIH Input logic-high leakage for digital inputs All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins,
input = IOVDD		 –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins,
input = 0 V		 –5 0.1 5 µA
VIL(GPIx) Low-level digital input logic voltage threshold PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation –0.3 0.35 × AVDD V
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation –0.3 0.8
VIH(GPIx) High-level digital input logic voltage threshold PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation 0.65 × AVDD AVDD + 0.3 V
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation 2 AVDD + 0.3
VOL(GPOx) Low-level digital output voltage PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2 mA, AVDD 1.8-V operation 0.45 V
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2 mA, AVDD 3.3-V operation 0.4
VOH(GPOx) High-level digital output voltage PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2 mA, AVDD 1.8-V operation AVDD – 0.45 V
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2 mA, AVDD 3.3-V operation 2.4
IIH(GPIx) Input logic-high leakage for digital inputs PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = AVDD –5 0.1 5 µA
IIL(GPIx) Input logic-high leakage for digital inputs PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = 0 V –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All external clocks stopped, AVDD = 3.3 V 5  µA
IAVDD All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10
IIOVDD All external clocks stopped, IOVDD = 3.3 V 0.5
IIOVDD All external clocks stopped, IOVDD = 1.8 V 0.3
IAVDD Current consumption with 4-channel PDM input recording AVDD = 3.3 V 9.1 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 8.1
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
IAVDD Current consumption with 4-channel PDM input recording, fS = 16 kHz, PDMCLKx = 96 × fS, PLL off and BCLK = 384 × fS AVDD = 3.3 V 7.3 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 6.3
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with no signal, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) The device performance parameters, SNR, DR and THD+N, are mainly limited by single-bit PDM modulator generated data output. The THD+N peformance for single-bit PDM modulator output itself is generally not so good for signal above –10-dB full-scale.