JAJSKU3D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

9.2.2 Detailed Design Procedure

The TLV841SADL01 can monitor any voltage above 0.505 V using an external voltage divider. This device has a negative going input threshold voltage of 0.505 V; however, the design needs to assert a reset when VDD drops below 2.90 V. By using a resistor divider (R1 = 47.5 kΩ, R2 = 10 kΩ) the negative going threshold voltage becomes 2.90 V. The device's positive going voltage threshold is VIT- + VHYS. The typical VHYS is 25 mV. This in combination with the resistor divider makes the design's positive going threshold voltage equal to 3.05 V. If VDD falls below 2.90 V, RESET will assert. If VDD rises above 3.05 V, RESET will deassert. See #GUID-9EC38A52-144D-47B5-AC20-187C5B72C024 for a timing diagram detailing the voltage levels and reset assertion/deassertion conditions.

Figure 9-2 Design 1 Timing Diagram

This design will also enter a reset condition when the "push-button input" is asserted. The push-button is tied to ground and when pressed will drop the SENSE voltage to 0 V, making the device assert a reset. As a good analog practice, a 0.1 µF capacitor was also placed on VDD.

The desired reset timing conditions are sense propagation delay time (tP_HL of 25 μs (how long it takes to assert RESET) and a reset delay time of 40 μs (how long it takes to deassert RESET). GUID-295ED977-492B-40D2-AE4E-E8F5F232EF28.html#SNVSBC359299-01 and GUID-295ED977-492B-40D2-AE4E-E8F5F232EF28.html#SNVSBC359299-1 are the results of the described application where the measured propagation delay and reset delay time are shown respectively.

For the requirement of a maximum output current, an external pull-up resistor needs to be selected so that the current through the external pull-up resistor exceeds no more than 150 µA. When the reset output is low, the voltage drop across the external pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum resistor value. The resistor needs to be greater than 22 kΩ in order to pull less than 150 µA in the reset asserted low condition. A resistor value of 30.1 kΩ was selected to accomplish this.

Note that this design does not account for tolerances.