JAJSKX7A July   2021  – December 2021 TCA9536

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 I2C Bus Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 P3 or Interrupt (INT) Output
      3. 8.3.3 Pull-up Disable Functionality
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 Writes
        2. 8.5.1.2 Reads
      2. 8.5.2 Software Reset Call
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIK Input diode clamp voltage II = -18 mA 1.65 V to 5.5 V –1.2 V
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.6 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V
VIH High-level input voltage SDA,SCL 1.65 to 5.5 V 0.7 × VCC V
VIH High-level input voltage P ports 1.65 to 5.5 V 0.7 × VCC V
VIL Low-level input voltage SDA,SCL 1.65 to 5.5 V 0.4 × VCC V
VIL Low-level input voltage P ports 1.65 to 5.5 V 0.3 × VCC V
VOH P-port high-level output voltage(1) IOH = -8 mA 1.65 V 1.2 V
2.3 V 1.8
3 V 2.6
4.5 V 4.1
4.75 V 4.1
IOH = -10 mA 1.65 V 1
2.3 V 1.7
3 V 2.5
4.5 V 4
4.75 V 4
IOL Low-level output current SDA VOL = 0.4 V 1.65 V to 5.5 V 20 mA
P0-P3 VOL = 0.5 V 8
VOL = 0.7 V 10
IOL Low-level output current INT(2) VOL = 0.4 V 1.65 V to 5.5 V 4 mA
II Input leakage current P ports VI = VCC 1.65 V to 5.5 V 0 ±1 µA
VI = 5.5 V ( TA ≤ 105 ℃) 0 V 0 ±1
VI = 5.5 V 0 V 0 ±2
VI = GND, PU Disabled 1.65 V to 5.5 V 0 ±1
II Input leakage current P ports VI = GND, PU Enabled 1.65 V to 5.5 V -100 -40 µA
II Input leakage current SCL, SDA input leakage VI = VCC or GND 1.65 V to 5.5 V 0 ±1 µA
ICC Quiescent current Operating mode VI = VCC or GND (PU Disabled), I/O = inputs, fSCL = 400 kHz, tr = tf = 300 ns 5.5 V 22 40 µA
3.6 V 11 20
2.7 V 8 10
1.95 V 5 8
ICC Quiescent current Operating mode VI = GND, I/O = inputs, fSCL = 400 kHz, tr = tf = 300 ns, PU Enabled 5.5 V 225 390 µA
3.6 V 175 280
2.7 V 125 200
1.95 V 100 150
ICC Quiescent current Operating mode VI  = VCC  or GND (PU Disabled), I/O = inputs, fSCL = 1 MHz, tr = tf = 120 ns 5.5 V 100 µA
3.6 V 40
2.7 V 25
1.95 V 15
ICC Quiescent current Operating mode VI = GND, I/O = inputs, fSCL = 1 MHz, tr = tf = 120 ns, PU Enabled 5.5 V 225 425 µA
3.6 V 175 250
2.7 V 125 200
1.95 V 100 150
ICC Quiescent current Standby mode VI = VCC, IO = 0, I/0 = inputs, fSCL = 0 kHz 5.5 V 1.5 3.9 µA
3.6 V 0.9 2.2
2.7 V 0.6 1.8
1.95 V 0.6 1.5
ICC Quiescent current Standby mode VI = GND, I/0 = inputs, fSCL = 0 kHz, PU Enabled 5.5 V 225 350 µA
3.6 V 175 250
2.7 V 125 200
1.95 V 100 150
CI Input pin capacitance SCL VI = VCC or GND 1.65 V to 5.5 V 4 5 pF
CIO Input-output pin capacitance SDA VIO = VCC or GND 1.65 V to 5.5 V 7 10 pF
P port VIO = VCC or GND 1.65 V to 5.5 V 7 10
(1) Each I/O must be externally limited to a maximum of 25 mA
(2) P3 can be repurposed as INT (open-drain interrupt output) in the special function register