JAJSKY8K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
MODE | OSPI_PHY_CONFIGURATION_REG BIT FIELD | DELAY VALUE |
---|---|---|
All modes | PHY_CONFIG_TX_DLL_DELAY_FLD | 0x0 |
PHY_CONFIG_RX_DLL_DELAY_FLD | 0x0 |
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
O19 | tsu(D-CLK) | Setup time, D[i:0] valid before active CLK edge(1) | 1.8V, Internal Loopback | -2.19 | ns | |
3.3V, Internal Loopback | -1.71 | ns | ||||
O20 | th(CLK-D) | Hold time, D[i:0] valid after active CLK edge(1) | 1.8V, Internal Loopback | 7.62 | ns | |
3.3V, Internal Loopbacl | 8.1 | ns | ||||
O21 | tsu(D-LBCLK) | Setup time, D[i:0] valid before active LBCLK input (DQS) edge(1) | 1.8V, External Board Loopback | -3.1 | ns | |
3.3V, External Board Loopback | -2.72 | ns | ||||
O22 | th(LBCLK-D) | Hold time, D[i:0] valid after active LBCLK input (DQS) edge(1) | 1.8V, External Board Loopback | 3.81 | ns | |
3.3V, External Board Loopback | 4.33 | ns |