JAJSKZ0A August   2021  – May 2022 ADC08DJ5200RF

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Comparison
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3 ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4 Temperature Monitoring Diode
      5. 7.3.5 Timestamp
      6. 7.3.6 Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7 Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8 JESD204C Interface
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Scrambler
        3. 7.3.8.3 Link Layer
        4. 7.3.8.4 8B/10B Link Layer
          1. 7.3.8.4.1 Data Encoding (8B/10B)
          2. 7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.8.4.3 Code Group Synchronization (CGS)
          4. 7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.8.4.5 Frame and Multiframe Monitoring
        5. 7.3.8.5 64B/66B Link Layer
          1. 7.3.8.5.1 64B/66B Encoding
          2. 7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.8.5.4 Initial Lane Alignment
          5. 7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.8.6 Physical Layer
          1. 7.3.8.6.1 SerDes Pre-Emphasis
        7. 7.3.8.7 JESD204C Enable
        8. 7.3.8.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.8.9 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 Clock Upset Detection
        2. 7.3.9.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
          3. 8.2.1.1.3 ADC08DJ5200RF
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 123
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 AAV Package, 144-Ball Flip Chip BGA, Top View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
AGNDA1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7—Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
BGC3OBand-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
CALSTATF7OForeground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIGE7IForeground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used.
CLK+F1IDevice (sampling) clock positive input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0.
CLK–G1IDevice (sampling) clock negative input. TI strongly recommends using AC-coupling for best performance.
DA0+E12OHigh-speed serialized data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA0–F12OHigh-speed serialized data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used.
DA1+C12OHigh-speed serialized data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA1–D12OHigh-speed serialized data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used.
DA2+A10OHigh-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA2–A11OHigh-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used.
DA3+A8OHigh-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA3–A9OHigh-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used.
DA4+E11OHigh-speed serialized data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA4–F11OHigh-speed serialized data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used.
DA5+C11OHigh-speed serialized data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA5–D11OHigh-speed serialized data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used.
DA6+B10OHigh-speed serialized data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA6–B11OHigh-speed serialized data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used.
DA7+B8OHigh-speed serialized data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA7–B9OHigh-speed serialized data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used.
DB0+H12OHigh-speed serialized data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB0–G12OHigh-speed serialized data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used.
DB1+K12OHigh-speed serialized data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB1–J12OHigh-speed serialized data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used.
DB2+M10OHigh-speed serialized data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB2–M11OHigh-speed serialized data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used.
DB3+M8OHigh-speed serialized data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB3–M9OHigh-speed serialized data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used.
DB4+H11OHigh-speed serialized data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB4–G11OHigh-speed serialized data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used.
DB5+K11OHigh-speed serialized data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB5–J11OHigh-speed serialized data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used.
DB6+L10OHigh-speed serialized data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB6–L11OHigh-speed serialized data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used.
DB7+L8OHigh-speed serialized data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB7–L9OHigh-speed serialized data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used.
DGNDA12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12—Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
INA+A4IChannel A analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INA–A5IChannel A analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
INB+M4IChannel B analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INB–M5IChannel B analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INB+ for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
NCOA0C7INot used. Tie this pin to GND.
NCOA1D7INot used. Tie this pin to GND.
NCOB0K7INot used. Tie this pin to GND.
NCOB1J7INot used. Tie this pin to GND.
ORA0C8OFast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORA1D8OFast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB0K8OFast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB1J8OFast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
PDK6IThis pin disables all analog circuits and serializer outputs when set high for temperature diode calibration or to reduce power consumption when the device is not being used. Tie this pin to GND if not used.
SCLKF8ISerial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SCSE8ISerial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ pullup resistor to VD11.
SDIG8ISerial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SDOH8OSerial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
SYNCSEC2ISingle-ended JESD204C SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do not use the SYNC signal for initialization, however it may be used for NCO synchronization. When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used as the JESD204C SYNC signal.
SYSREF+K1IThe SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table.
SYSREF–L1ISYSREF negative input
TDIODE+K2ITemperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
TDIODE–K3ITemperature diode negative (cathode) connection. This pin can be left disconnected if not used.
TMSTP+B1ITimestamp input positive connection or differential JESD204C SYNC positive connection. This input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1. This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as a JESD204C SYNC. For additional usage information, see the Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC and DC coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required.
TMSTP–C1ITimestamp input positive connection or differential JESD204C SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required.
VA11C5, D2, D3, D5, E5, F5, G5, H5, J2, J3, J5, K5I1.1-V analog supply
VA19C4, D4, E2, E3, E4, F4, G4, H2, H3, H4, J4, K4I1.9-V analog supply
VD11C9, C10, E9, E10, G7, H7, H9, H10, K9, K10I1.1-V digital supply