JAJSKZ0A August   2021  – May 2022 ADC08DJ5200RF

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Comparison
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3 ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4 Temperature Monitoring Diode
      5. 7.3.5 Timestamp
      6. 7.3.6 Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7 Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8 JESD204C Interface
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Scrambler
        3. 7.3.8.3 Link Layer
        4. 7.3.8.4 8B/10B Link Layer
          1. 7.3.8.4.1 Data Encoding (8B/10B)
          2. 7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.8.4.3 Code Group Synchronization (CGS)
          4. 7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.8.4.5 Frame and Multiframe Monitoring
        5. 7.3.8.5 64B/66B Link Layer
          1. 7.3.8.5.1 64B/66B Encoding
          2. 7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.8.5.4 Initial Lane Alignment
          5. 7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.8.6 Physical Layer
          1. 7.3.8.6.1 SerDes Pre-Emphasis
        7. 7.3.8.7 JESD204C Enable
        8. 7.3.8.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.8.9 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 Clock Upset Detection
        2. 7.3.9.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
          3. 8.2.1.1.3 ADC08DJ5200RF
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 123
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics: DC Specifications

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.2 GHz, filtered 1-VPP sine-wave clock, JMODE = 6, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
Resolution Resolution with no missing codes 8 Bits
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.08 LSB
Maximum negative excursion from ideal step size –0.08
INL Integral nonlinearity Maximum positive excursion from ideal transfer function 0.1 LSB
Maximum negative excursion from ideal transfer function –0.15 LSB
ANALOG INPUTS (INA+, INA–, INB+, INB–)
VOFF Offset error CAL_OS = 0 ±0.50 mV
CAL_OS = 1 ±0.15 mV
VOFF_ADJ Input offset voltage adjustment range Available offset correction range (see OS_CAL or OADJ_x_INx) ±50 mV
VOFF_DRIFT Offset drift Foreground calibration at nominal temperature only 11 µV/°C
Foreground calibration at each temperature -2.7
Foreground and FGOS calibration at each temperature 0
VFS Analog differential input full-scale range Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) 775 825 875 mVPPDIFF
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) 1000 1060
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) 500 550
VFS_DRIFT Analog differential input full-scale range drift Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by a 50-Ω source, includes effect of RIN drift 0.055 %/°C
VFS_MATCH Analog differential input full-scale range matching Matching between INA± and INB±, default setting, dual-channel mode 0.4%
RIN Single-ended input resistance to AGND Each input pin is terminated to AGND, measured at TA = 25°C 48 50 52 Ω
RIN_TEMPCO Input termination linear temperature coefficient 14.7 mΩ/°C
CIN Single-ended input capacitance Single-channel mode measured at DC 0.4 pF
Dual-channel mode measured at DC 0.4
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement must be done with the device unpowered or with the PD pin asserted to minimize device self-heating. –1.65 mV/°C
BAND-GAP VOLTAGE OUTPUT (BG)
VBG Reference output voltage IL ≤ 100 µA 1.1 V
VBG_DRIFT Reference output temperature drift IL ≤ 100 µA –123 µV/°C
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
ZT Internal termination Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 100 Ω
Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 50
VCM Input common-mode voltage, self-biased Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0) 0.3 V
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1) 0.28
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0) 0.28
CL_DIFF Differential input capacitance Between positive and negative differential input pins 0.04 pF
CL_SE Single-ended input capacitance Each input to ground 0.5 pF
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
VOD Differential output voltage, peak-to-peak 100-Ω load 550 600 650 mVPP-DIFF
VCM Output common-mode voltage AC coupled VD11 / 2 V
ZDIFF Differential output impedance 100 Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
VIH High-level input voltage required input voltage 0.7 V
VIL Low-level input voltage required input voltage 0.45 V
IIH High-level input current 40 µA
IIL Low-level input current –40 µA
CI Input capacitance 3.4 pF
VOH High-level output voltage ILOAD = –400 µA 1.65 V
VOL Low-level output voltage ILOAD = 400 µA 150 mV