JAJSL42H January   2020  – May 2022 ISO6720-Q1 , ISO6721-Q1 , ISO6721R-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6.     Insulation Specifications
    7. 7.6  Safety-Related Certifications
    8. 7.7  Safety Limiting Values
    9.     Electrical Characteristics—5-V Supply
    10. 7.8  Supply Current Characteristics—5-V Supply
    11. 7.9  Electrical Characteristics—3.3-V Supply
    12. 7.10 Supply Current Characteristics—3.3-V Supply
    13. 7.11 Electrical Characteristics—2.5-V Supply 
    14. 7.12 Supply Current Characteristics—2.5-V Supply
    15.     Electrical Characteristics—1.8-V Supply
    16. 7.13 Supply Current Characteristics—1.8-V Supply
    17. 7.14 Switching Characteristics—5-V Supply
    18. 7.15 Switching Characteristics—3.3-V Supply
    19. 7.16 Switching Characteristics—2.5-V Supply
    20. 7.17 Switching Characteristics—1.8-V Supply
    21. 7.18 Insulation Characteristics Curves
    22. 7.19 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 Insulation Lifetime
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

Insulation Specifications

PARAMETER TEST CONDITIONS VALUE VALUE UNIT
8-DWV 8-D
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >8.5 >4 mm
CPG External creepage(1) Side 1 to side 2 distance across package surface >8.5 >4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 >400 V
Material Group According to IEC 60664-1 I II
Overvoltage category Rated mains voltage ≤ 150 VRMS I–IV I-IV
Rated mains voltage ≤ 300 VRMS I–IV I-III
Rated mains voltage ≤ 600 VRMS I–IV n/a
Rated mains voltage ≤ 1000 VRMS I-III n/a
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 637 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test. See Figure 10-9 1060 450 VRMS
DC voltage 1500 637 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7071 4242 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform,
DWV: VTEST = 1.6 × VIOSM = 10,000 VPK (qualification), 
D: VTEST = 1.3 × VIOSM = 6,500 VPK (qualification)		 6250 5000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
DWV: Vpd(m) = 1.6 × VIORM , tm = 10 s
D: Vpd(m) = 1.2 × VIORM , tm = 10 s		 ≤ 5 ≤ 5
Method b: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
DWV: Vpd(m) = 1.875 × VIORM , tm = 1 s
D: Vpd(m) = 1.5 × VIORM , tm = 1 s		 ≤ 5 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz ~0.5 ~0.5 pF
RIO Insulation resistance, input to output(5) VIO = 500 V,  TA = 25°C > 1012 > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C > 1011 > 1011
VIO = 500 V at  TS = 150°C > 109 > 109
Pollution degree 2 2
Climatic category
40/125/21

 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 5000 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation (ISO672x) and basic electrical insulation (ISO672xB) only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.