JAJSL62 February   2021 INA183

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Single-Supply Operation from IN+
      2. 8.3.2 Low Gain Error and Offset Voltage
      3. 8.3.3 Low Drift Architecture
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Unidirectional, High-Side Operation
      3. 8.4.3 Input Differential Overload
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 RSENSE and Device Gain Selection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

8.2 Functional Block Diagram

The simplified functional diagram below shows the device power is provided by the voltage on the IN+ pin. This diagram also shows the nominal values for the internal gain set resistors. The nominal value of these resistors can vary by 20% or more; however, the matching between these resistors is tightly controlled. The matching of these internal resistors results in a precise fixed gain that varies very little over temperature.

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