JAJSL82 December   2021 AMC1350-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 What To Do and What Not To Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

6.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output signal rise time 1.3 µs
tf Output signal fall time 1.3 µs
IN to OUTx signal delay (50% – 10%) Unfiltered output 1 1.5 µs
IN to OUTx signal delay (50% – 50%) Unfiltered output 1.6 2.1 µs
IN to OUTx signal delay (50% – 90%) Unfiltered output 2.5 3 µs
tAS Analog settling time VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to VOUTP and VOUTN valid, 0.1% settling 500 800 µs