JAJSLC6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

7.4.12.6 Programmable Over-Power Protection (OPP)

The over-power protection (OPP) allows operation in an over-power condition for a limited amount of time, so the UCC28781-Q1 can support a power stage design with temporary peak power requirements. As shown in #T4924628-52, when VCST is higher than the threshold voltage of the OPP curve (VCST(OPP)), a 160-ms timer starts. For the auto-recovery mode, if VCST remains higher than VCST(OPP) continuously for 160 ms, the 1.5-s timer starts and the controller stays in fault state without switching. This long recovery time reduces the average current during a sustained over-power event. The system benefits includes the reduction of thermal stress in high density adapters and the protection of its output cable.

The OPP function uses IVSL as a line feed-forward signal to vary VCST(OPP) depending on VBULK, in order to make the OPP trigger point constant over a wide line voltage range. The UCC28781-Q1 allows programmability of the OPP curve by adding a line-compensation offset voltage on the CS pin through a resistor (ROPP) connected between the CS pin and current-sense resistor (RCS). An internal current source flowing out of CS pin creates the offset voltage on ROPP. This current level is equal to IVSL divided by a constant gain of KLC. As ROPP increases, the OPP trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run continuously.

The OPP function uses VVS as an output voltage feed-forward signal to modify the line-dependent VCST(OPP) curve into the two different sets, such that the OPP trigger point can be more consistent across a wide output voltage range. The higher OPP threshold under VVS > 2.5 V contains two piece-wise linear regions, and the lower OPP threshold under VVS < 2.4 V contains one piece-wise linear region.

The highest threshold of OPP curve (VCST(OPP1)) of 0.6 V helps to determine RCS value at VBULK(MIN) .

Equation 17. GUID-B486D991-D1B2-4FF6-911A-CDB7D75DAF73-low.gif

where PO(OPP) is the output power that triggers OPP, and tD(CST) is the sum of all delays in the peak current loop which contributes additional peak current overshoot. tD(CST) consists of propagation delay of the low-side driver, current sense filter delay (ROPP x CCS), internal CS comparator delay (tD(CS)), and nonlinear capacitance delay of QL. After RCS is determined, ROPP can be adjusted to keep a similar OPP point at highest line. Note that setting the OPP trigger point too far away from the full power may introduce more challenge on the thermal design, since the converter runs continuously with more power as long as the corresponding peak current is slightly less than OPP threshold.

GUID-49495E2B-E029-45B6-8E43-554EF7D4D50F-low.gifFigure 7-43 VCST OPP curve across IVSL
GUID-0E7A2B8D-62CD-4750-B756-9136B7641B02-low.gifFigure 7-44 Timing Diagram of OPP