JAJSLC9A February   2021  – August 2021 TCA9416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Enable and Disable
      3. 8.3.3 Pull up resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Startup Considerations with Large Capacitive Load Mismatches
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary

8.1 Overview

The TCA9416 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A and B ports are able to accept I/O voltages ranging from 1.08 V to 3.6 V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to improve the overall data rate. 10-kΩ pull up resistors, commonly used in open-drain applications, have been conveniently integrated so that an external resistor is not needed. When TCA9416 is disabled the one shots are also disabled, but the internal pull ups are still enabled. Pull up resistors are gated on the supply voltage. When supply is above UVLO, the pull up resistor for that specific side (A vs B) is enabled.