JAJSLC9A February   2021  – August 2021 TCA9416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Enable and Disable
      3. 8.3.3 Pull up resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Startup Considerations with Large Capacitive Load Mismatches
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary

8.3.1 Architecture

The TCA9416 architecture (see Figure 8-1) is an auto-direction-sensing based translator that does not require a direction-control signal to control the direction of data flow from A to B or from B to A.

Figure 8-1 Architecture of a TCA9416 Cell

These two bidirectional channels support both directions of data flow without a direction-control signal. By properly biasing the gate of the pass-FET, the FET can turn on (low RDSON), when either side input voltage drops to ~ 1 voltage threshold below the lowest of the two supplies.

The TCA9416 is part of the TI "Switch" type voltage translator family and employs key circuits to enable this voltage translation:

  1. An N-channel pass-gate transistor topology that ties the A-port to the B-port.
  2. Output rise time accelerator circuitry to detect and accelerate rising edges on the A or B ports
  3. Output fall time accelerator circuitry to detect and accelerate falling edges on the A or B ports

For bidirectional voltage translation, pull up resistors are included on the device for dc current sourcing capability. The VGATE gate bias of the N-channel pass transistor is set to the lower supply voltage and can be represented with MIN(VCCA, VCCB).

The rise and fall time accelerator (RTA and FTA, respectively) circuitry speeds up the output slew rate by monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the rise time accelerator (RTA) circuit turns on to increase the current drive capability of the driver. This edge-rate acceleration provides high ac drive by bypassing the internal 10-kΩ pull up resistors during the low-to-high transition to speed up the signal. The output resistance of the driver is decreased to approximately 150 Ω during this acceleration phase. During a high-to-low signal falling edge, the fall time accelerator (FTA) turns on to increase the current drive capability of the driver, similar to the rise time accelerator. This helps reduce the fall time for large capacitive loads. For light capacitive loads, the fall time accelerator will not enable.

Both the rise and fall time accelerators have logic to control the rate at which they turn on and off, in order to reduce ringing and over/undershoots.