For best operational performance of the device, follow PCB layout best practices, including:

• Connect 0.1µF ceramic bypass capacitors with low equivalent series resistance (ESR) between each supply pin and ground. Place the capacitors as close to the device as possible. For single-supply applications, use a single bypass capacitor from V+ to ground. Bypass capacitors are used to reduce coupled noise by providing low-impedance power sources local to the analog circuitry.
• Physically separate digital and analog grounds, paying attention to the flow of the ground current. Separate grounding for analog and digital circuitry is one of the simplest and most effective methods for noise suppression. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
• Place external components as close to the device as possible.
• Keep the length of input traces as short as possible. Input traces are the most sensitive part of the circuit.

In addition to general PCB layout considerations, specific layout techniques must be implemented to achieve femtoampere-level input bias current. Every insulator, including PCB material, has a finite resistance that can become a path for current to leak into input traces and degrade input bias performance. To minimize leakage current paths, implement a guard in the PCB layout. The guard presents a low-impedance path equipotential to the input traces. Leakage current toward the high impedance input path can be diverted to the low-impedance guard path. Current flowing between the input and guard traces is negligible because both traces are at the same potential. See also Section 7.1.2.

Surround all high-impedance input traces with copper guard traces all the way from the source to the input pins of the OPA928. For inverting configurations, extend the guard copper to the middle of the feedback components, separating the low-impedance output from the high-impedance input node. Remove all solder mask and silkscreen from the guard area to reduce surface-charge accumulation and prevent surface-level leakage paths to the input.

Leakage currents can flow between layers vertically or diagonally through the PCB, as well as horizontally on the surface layer. The guard must be implemented in a three-dimensional scheme to prevent leakage currents originating in other layers from flowing into the signal path. Place the guard copper on the next layer directly below the surface-level signal and guard traces to protect from vertical leakage paths. Surround the sensitive input traces with a via fence connecting the guard copper on different layers to complete the three-dimensional guard enclosure. Figure 7-23 shows the internal copper layers of a four-layer PCB using a three-dimensional guarding scheme.

A copper ground pour around the OPA928 and guard area is recommended to reduce noise and EMI. In addition to noise and EMI benefits, this ground pour presents another low-impedance path for leakage currents to take. Keep voltage potentials other than guard and ground as far as possible from sensitive nodes. The OPA928 SOIC pinout places the input and power supply pins at opposite ends of the amplifier package to reduce leakage currents across the package and PCB material. If the power supplies (or other voltages) are present in vias or through-holes near the OPA928, a ground-potential via fence can be applied locally to these through-holes to provide a low-impedance path for leakage currents in the direction of sensitive nodes.

High-impedance, femtoampere-level circuits are highly sensitive to EMI. Ground planes and ground pours in the PCB layout can help reduce the effects of EMI. During operation, a femtoampere-level PCB is commonly placed within a shielded enclosure tied to ground for further EMI rejection. In layout, consider enclosing the OPA928 and all high-impedance traces within a local grounded RF shield. An example of localized RF shielding for high-impedance nodes is available in the OPA928 Evaluation Module User's Guide.