JAJSLW9B May   2020  – January 2023 BQ25798

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power-On-Reset
      2. 9.3.2  PROG Pin Configuration
      3. 9.3.3  Device Power Up from Battery without Input Source
      4. 9.3.4  Device Power Up from Input Source
        1. 9.3.4.1 Power Up REGN LDO
        2. 9.3.4.2 Poor Source Qualification
        3. 9.3.4.3 ILIM_HIZ Pin
        4. 9.3.4.4 Default VINDPM Setting
        5. 9.3.4.5 Input Source Type Detection
          1. 9.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 9.3.4.5.2 HVDCP Detection Procedure
          3. 9.3.4.5.3 Connector Fault Detection
      5. 9.3.5  Dual-Input Power Mux
        1. 9.3.5.1 ACDRV Turn On Condition
        2. 9.3.5.2 VBUS Input Only
        3. 9.3.5.3 One ACFET-RBFET
        4. 9.3.5.4 Two ACFETs-RBFETs
      6. 9.3.6  Buck-Boost Converter Operation
        1. 9.3.6.1 Force Input Current Limit Detection
        2. 9.3.6.2 Input Current Optimizer (ICO)
        3. 9.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 9.3.6.4 Pulse Frequency Modulation (PFM)
        5. 9.3.6.5 Device HIZ State
      7. 9.3.7  USB On-The-Go (OTG)
        1. 9.3.7.1 OTG Mode to Power External Devices
        2. 9.3.7.2 Backup Power Supply Mode
        3. 9.3.7.3 Backup Mode with Dual Input Mux
      8. 9.3.8  Power Path Management
        1. 9.3.8.1 Narrow VDC Architecture
        2. 9.3.8.2 Dynamic Power Management
      9. 9.3.9  Battery Charging Management
        1. 9.3.9.1 Autonomous Charging Cycle
        2. 9.3.9.2 Battery Charging Profile
        3. 9.3.9.3 Charging Termination
        4. 9.3.9.4 Charging Safety Timer
        5. 9.3.9.5 Thermistor Qualification
          1. 9.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 9.3.10 Integrated 16-Bit ADC for Monitoring
      11. 9.3.11 Status Outputs ( STAT, and INT)
        1. 9.3.11.1 Charging Status Indicator (STAT Pin)
        2. 9.3.11.2 Interrupt to Host ( INT)
      12. 9.3.12 Ship FET Control
        1. 9.3.12.1 Shutdown Mode
        2. 9.3.12.2 Ship Mode
        3. 9.3.12.3 System Power Reset
      13. 9.3.13 Protections
        1. 9.3.13.1 Voltage and Current Monitoring
          1. 9.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 9.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 9.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 9.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 9.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 9.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 9.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 9.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 9.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 9.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 9.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 9.3.14 Serial Interface
        1. 9.3.14.1 Data Validity
        2. 9.3.14.2 START and STOP Conditions
        3. 9.3.14.3 Byte Format
        4. 9.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.14.5 Target Address and Data Direction Bit
        6. 9.3.14.6 Single Write and Read
        7. 9.3.14.7 Multi-Write and Multi-Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
      2. 9.4.2 Register Bit Reset
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PV Panel Selection
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input (VBUS / PMID) Capacitor
        4. 10.2.2.4 Output (VSYS) Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

9.3.7.1 OTG Mode to Power External Devices

The device supports the OTG operation to deliver power from the battery to other external devices through the USB ports. The OTG voltage regulation is set in VOTG[10:0] register bits. The OTG current regulation is set in IOTG[6:0] register bits. To enable the OTG operation, the following conditions have to be valid:

  • The battery voltage is higher than VBAT_OTG rising threshold, and not trigger the VBAT_OVP protection.
  • The VBUS is below VVBUS_UVLO.
  • The voltage at TS pin is within the range configured by BHOT and BCOLD register bits

The population of ACFET1-RBFET1 and ACFET2-RBFET2 as detected at POR affects the operation of the converter in OTG mode as summarized in Table 9-8.

Table 9-8 OTG Behavior by Input Mux State
ACRB1_STAT ACRB2_STAT DIS_ACDRV OTG BEHAVIOR
0 0 0 Converter starts 5 ms after EN_OTG = 1
0 1 0 EN_OTG = 1 does not start converter until EN_ACDRV2 = 1
1 0 0 EN_OTG = 1 does not start converter until EN_ACDRV1 = 1
1 1 0 EN_OTG = 1 does not start converter until either EN_ACDRV1 = 1 or EN_ACDRV2 = 1
X X 1 Converter starts 5 ms after EN_OTG = 1

For swapping the OTG output from port 1 to port 2, assuming EN_ACDRV2 is already 0, the host has to set EN_ACDRV1 = 0 to turn off ACFET1_RBFET1 first, which causes the converter to stop switching and VBUS to drop below VBUS_PRESENT. The host then sets EN_ACDRV2 = 1, and the converter starts switching again and ACDRV2 turns on ACFET2-RBFET2, which allows VBUS to ramp up. The similar procedure can be applied to the case of swapping the OTG output from port 2 to port 1.

In OTG mode, the converter PFM operation can be disabled by setting PFM_OTG_DIS = 1 and the OOA can be disabled by setting DIS_OTG_OOA = 1.

GUID-48571562-E13A-49C9-9981-5E90EDE39BAF-low.gif Figure 9-5 The Simplified Application Diagram for the OTG Mode Operation

The simplified application diagram for the OTG mode operation is shown in Figure 9-5, in which the power flow is illustrated by the blue arrows.

The charger regulates the battery discharging current in OTG mode. When IBAT rises higher than the IBAT_REG[1:0] register setting, the charger reduces the OTG output current and prioritizes the system load current if there is any. The IBAT_REG_STAT bit is set to 1 and an INT pulse is asserted, and if IBAT_REG_MASK = 0, the IBAT_REG_FLAG is set to 1. If the OTG output current is decreased to zero and the system load pulls even more current, the charger can no longer limit the battery discharging current.

When IBAT_REG[1:0] is set to 00, 01 or 10 (3A, 4A or 5A), there is a soft-start applied to the OTG ouput current. When IBAT_REG[1:0] is set to 11 (Disabled) no soft-start is applied.