JAJSM11 may   2021 BQ25720

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (SMBus address = 21h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 9.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 9.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
      11. 9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
      19. 9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
      21. 9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

8.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINPUT_OP Input voltage operating range 3.5 26 V
MAX SYSTEM VOLTAGE REGULATION
VSYSMAX_RNG System Voltage Regulation, measured on VSYS (charge disabled) 1.024 19.2 V
VSYSMAX_ACC System voltage regulation accuracy (charge disabled and EN_OOA=0b) REG0x15() = 0x41A0H (16.800 V) VSRN + 150 mV V
–2% 2%
REG0x15() = 0x3138H (12.600 V) VSRN + 150 mV V
–2% 2%
REG0x15() = 0x20D0H (8.400 V) VSRN + 150 mV V
–3% 3%
REG0x15() = 0x1068H (4.200 V) VSRN + 150 mV V
–3% 3%
MINIMUM SYSTEM VOLTAGE REGULATION
VSYS_MIN_RNG System Voltage Regulation, measured on VSYS 1.00 19.2 V
VSYS_MIN_REG_ACC Minimum System Voltage Regulation Accuracy (VBAT below REG0x3E() setting, EN_OOA=0b) REG0x3E() = 0x7B00H 12.30 V
–2% –2%
REG0x3E() = 0x5C00H 9.20 V
–2% –2%
REG0x3E() = 0x4200H 6.60 V
–3% –3%
REG0x3E() = 0x2400H 3.60 V
–3% –3%
CHARGE VOLTAGE REGULATION
VBAT_RNG Battery voltage regulation 1.024 19.2 V
VBAT_REG_ACC Battery voltage regulation accuracy (charge enable) (0°C to 85°C) REG0x15() = 0x41A0H 16.8 V
–0.5% 0.5%
REG0x15() = 0x3138H 12.6 V
–0.5% 0.5%
REG0x15() = 0x20D0H 8.4 V
–0.6% 0.6%
REG0x15() = 0x1068H 4.2 V
–1.1% 1.2%
CHARGE CURRENT REGULATION IN FAST CHARGE
VIREG_CHG_RNG Charge current regulation differential voltage range VIREG_CHG = VSRP – VSRN 0 81.28 mV
ICHRG_REG_ACC Charge current regulation accuracy 10-mΩ sensing resistor, VBAT above 0x3E() setting (0°C to 85°C) REG0x14() = 0x1000H 4096 mA
–3.0% 2.0%
REG0x14() = 0x0800H 2048 mA
–4.0% 3.0%
REG0x14() = 0x0400H 1024 mA
–5.0% 6.0%
REG0x14() = 0x0200H 512 mA
–12.0% 12.0%
CHARGE CURRENT REGULATION IN LDO MODE
ICLAMP Pre-charge current clamp CELL(≥2 S) VSRN < VSYS_MIN 384 mA
CELL 1 S, VSRN < 3 V 384 mA
CELL 1 S, 3 V < VSRN < VSYS_MIN 2 A
IPRECHRG_REG_ACC Pre-charge current regulation accuracy with 10-mΩ SRP/SRN series resistor, VBAT below VSYS_MIN(REG0x3E()) setting (0°C to 85°C) REG0x14() = 0x0180H 384 mA
≥2S –15.0% 15.0%
1S –25.0% 25.0%
REG0x14() = 0x0100H 256 mA
≥2S –20.0% 20.0%
1S –35.0% 35.0%
REG0x14() = 0x00C0H 192 mA
≥2S –25.0% 25.0%
1S –50.0% 50.0%
REG0x14() = 0x0080H 128 mA
≥2S –30.0% 30.0%
ILEAK_SRP_SRN SRP, SRN leakage current mismatch (0°C to 85°C) –13.5 10.0 µA
INPUT CURRENT REGULATION
VIREG_DPM_RNG Input current regulation differential voltage range with 10-mΩ ACP/ACN series resistor VIREG_DPM = VACP – VACN 0.5 64 mV
IIIN_DPM_REG_ACC Input current regulation accuracy (-40°C to 105°C) with 10-mΩ ACP/ACN series resistor REG0x3F() = 0x4E00H 3800 3900 4000 mA
REG0x3F() = 0x3A00H 2800 2900 3000 mA
REG0x3F() = 0x1C00H 1300 1400 1500 mA
REG0x3F() = 0x0800H 300 400 500 mA
ILEAK_ACP_ACN ACP, ACN leakage current mismatch –21 10 µA
VIREG_DPM_RNG_ILIM Voltage range for input current regulation (ILIM_HIZ Pin) 1.15 4 V
IIIN_DPM_REG_ACC_ILIM Input Current Regulation Accuracy on ILIM_HIZ pin VILIM_HIZ = 1 V + 40 × IDPM × RAC, with 10-mΩ ACP/ACN series resistor VILIM_HIZ = 2.6 V 3800 4000 4200 mA
VILIM_HIZ = 2.2 V 2800 3000 3200 mA
VILIM_HIZ = 1.6 V 1300 1500 1700 mA
VILIM_HIZ = 1.2 V 300 500 700 mA
ILEAK_ILIM ILIM_HIZ pin leakage current –1 1 µA
INPUT VOLTAGE REGULATION
VDPM_RNG Input voltage regulation range Voltage on VBUS 3.2 19.52 V
VDPM_REG_ACC Input voltage regulation accuracy REG0x3D()=0x3C80H 18688 mV
–3% 2%
REG0x3D()=0x1E00H 10880 mV
–4% 2.5%
REG0x3D()=0x0500H 4480 mV
–5.2% 5.0%
OTG CURRENT REGULATION
VIOTG_REG_RNG OTG output current regulation differential voltage range VIOTG_REG = VACP – VACN 0 81.28 mV
IOTG_ACC OTG output current regulation accuracy with 50-mA LSB and 10-mΩ ACP/ACN series resistor REG0x3C() = 0x3C00H 2800 3000 3200 mA
REG0x3C() = 0x1E00H 1300 1500 1700 mA
REG0x3C() = 0x0A00H 300 500 700 mA
OTG VOLTAGE REGULATION
VOTG_REG_RNG OTG voltage regulation range(OOA disabled) Voltage on VBUS 3 24.00 V
VOTG_REG_ACC OTG voltage regulation accuracy(OOA disabled) REG0x3B()=0x2CEC 23.00 V
–2% 2%
REG0x3B()=0x1770H 12.00 V
–2% 2%
REG0x3B()=0x09C4H 5.00 V
–3% 3%
REGN REGULATOR
VREGN_REG REGN regulator voltage (0 mA – 60 mA) VVBUS = 10 V 5.7 6 6.3 V
VDROPOUT REGN voltage in drop out mode VVBUS = 5 V, ILOAD = 20 mA 3.8 4.3 4.6 V
IREGN_LIM_Charging REGN current limit when converter is enabled VVBUS = 10 V, force VREGN =4 V 50 65 mA
QUIESCENT CURRENT
IBAT_BATFET_ON System powered by battery. BATFET on. ISRN + ISRP + ISW2 + IBTST2 + ISW1 + IBTST1 + IACP + IACN + IVBUS + IVSYS VBAT = 18 V, REG0x12[15] = 1,REG0x30[14] = 0b, in low-power mode, Disable PSYS 22 45 µA
VBAT = 18 V, REG0x12[15] = 1, REG0x30[14] = 1b, REG0x30[13:12] = 11b,REGN off, Disable PSYS, Enable low power PROCHOT 35 60 µA
VBAT = 18 V, REG0x12[15]= 0,REG0x30[13:12]= 11b, REGN on, Disable PSYS, In performance mode 880 1170 µA
VBAT = 18 V, REG0x12[15] = 0, REG0x30[13:12] = 00b, REGN on, Enable PSYS, In performance mode 980 1270 µA
IAC_SW_LIGHT_buck Input current during PFM in buck mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST + ISW2 + IBTST2 VIN = 20 V, VBAT = 12.6 V, 3s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.2 mA
IAC_SW_LIGHT_boost Input current during PFM in boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2 VIN = 5 V, VBAT = 8.4 V, 2s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.7 mA
IAC_SW_LIGHT_buckboost Input current during PFM in buck boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST1 + ISW2 + IBTST2 VIN = 12 V, VBAT = 12 V, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.4 mA
IOTG_STANDBY Quiescent current during PFM in OTG mode IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2 VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching frequency, MOSFET Qg = 4nC 3 mA
VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching frequency, MOSFET Qg = 4nC 4.2 mA
VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching frequency, MOSFET Qg = 4nC 6.2 mA
CURRENT SENSE AMPLIFIER
VACP_ACN_OP Input common mode range Voltage on ACP/ACN 3.8 26 V
VIADPT_CLAMP IADPT output clamp voltage 3.1 3.2 3.3 V
IIADPT IADPT output current 1 mA
AIADPT Input current sensing gain V(IADPT) / V(ACP-ACN), REG0x12[4] = 0 20 V/V
V(IADPT) / V(ACP-ACN), REG0x12[4] = 1 40 V/V
VIADPT_ACC Input current monitor accuracy V(ACP-ACN) = 40.96 mV –2% 2%
V(ACP-ACN) = 20.48 mV –3% 3%
V(ACP-ACN) =10.24 mV –6% 6%
V(ACP-ACN) = 5.12 mV –10% 10%
CIADPT_MAX Maximum capacitance at IADPT Pin 100 pF
VSRP_SRN_OP Battery common mode range Voltage on SRP/SRN 2.5 19.2 V
VIBAT_CLAMP IBAT output clamp voltage 3.05 3.2 3.3 V
IIBAT IBAT output current 1 mA
AIBAT Charge and discharge current sensing gain on IBAT pin V(IBAT) / V(SRN-SRP), REG0x12[3] = 0, 8 V/V
V(IBAT) / V(SRN-SRP), REG0x12[3] = 1, 16 V/V
IIBAT_CHG_ACC Charge and discharge current monitor accuracy on IBAT pin V(SRN-SRP) = 40.96 mV –2% 2%
V(SRN-SRP) = 20.48 mV –4% 4%
V(SRN-SRP) =10.24 mV –7% 7%
V(SRN-SRP) = 5.12 mV –15% 15%
CIBAT_MAX Maximum capacitance at IBAT Pin 100 pF
SYSTEM POWER SENSE AMPLIFIER
VPSYS PSYS output voltage range 0 3.3 V
IPSYS PSYS output current 0 160 µA
APSYS PSYS system gain I(PSYS) / (P(IN) +P(BAT)), REG0x30[13:12] = 00b;REG0x30[9] = 1b 1 µA/W
APSYS PSYS system gain I(PSYS) / P(IN), REG0x30[13:12]= 01b;REG0x30[9] = 1b 1 µA/W
VPSYS_ACC PSYS gain accuracy (REG0x30[13:12] = 00b) Adapter only with system power = 19.5 V / 45 W, TA = 0 to 85°C –4% 4%
Battery only with system power = 11 V / 44 W, TA = 0 to 85°C –3% 3%
PSYS gain accuracy (REG0x30[13:12] = 01b) Adapter only with system power = 19.5 V / 45 W, TA = 0 to 85°C –4% 4%
VPSYS_CLAMP PSYS clamp voltage 3 3.3 V
VMIN ACTIVE PROTECTION(VAP) PROCHOT COMPARATOR
VSYS_TH1Z VAP VSYS rising threshold 1 VSYS_TH1 rising 6.4 6.6 6.75 V
VSYS_TH1 VAP VSYS falling threshold 1 VSYS_TH1 falling REG33<7:2>=100010b 6.3 6.5 6.65 V
VSYS_TH1_HYST VAP VSYS threshold 1 hysteresis 100 mV
tSYS_TH1_falling_DEG VSYS threshold 1 falling deglitch for VAP shooting 4 us
VSYS_TH2Z VAP VSYS rising threshold 2 VSYS_TH2 rising 6.1 6.3 6.45 V
VSYS_TH2 VAP VSYS falling threshold 2 VSYS_TH2 falling REG37<7:2>=011111b 6.0 6.2 6.35 V
VSYS_TH2_HYST VAP VSYS threshold 2 hysteresis 100 mV
tSYS_TH2_falling_DEG VSYS threshold 2 falling deglitch for throttling 4 us
VBUS_VAP_THZ VAP mode VBUS rising threshold VBUS_VAP_TH rising 3.15 3.35 3.50 V
VBUS_VAP_TH VAP mode VBUS falling threshold VBUS_VAP_TH falling REG37<15:9>=0000000b 3.0 3.2 3.35 V
VBUS_VAP_TH_HYST VAP mode VBUS threshold hysteresis 150 mV
tBUS_VAP_TH_falling_DEG VBUS falling deglitch for throttling 4 us
VSYS UNDER VOLTAGE LOCKOUT COMPARATOR
VSYS_UVLOZ VSYS undervoltage rising threshold(≥1S) VSYS rising 2.3 2.5 2.65 V
VSYS_UVLO VSYS undervoltage falling threshold(≥1S) VSYS falling REG36<15:13>=000b 2.2 2.4 2.55 V
VSYS_UVLO_HYST VSYS undervoltage hysteresis(≥1S) 100 mV
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VVBUS_UVLOZ VBUS undervoltage rising threshold VBUS rising 2.35 2.55 2.80 V
VVBUS_UVLO VBUS undervoltage falling threshold VBUS falling 2.2 2.4 2.6 V
VVBUS_UVLO_HYST VBUS undervoltage hysteresis 150 mV
VVBUS_CONVEN VBUS converter enable rising threshold VBUS rising 3.2 3.5 3.9 V
VVBUS_CONVENZ VBUS converter enable falling threshold VBUS falling 2.9 3.2 3.5 V
VVBUS_CONVEN_HYST VBUS converter enable hysteresis 300 mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VVBAT_UVLOZ VBAT undervoltage rising threshold VSRN rising 2.35 2.55 2.80 V
VVBAT_UVLO VBAT undervoltage falling threshold VSRN falling 2.2 2.4 2.6 V
VVBAT_UVLO_HYST VBAT undervoltage hysteresis 150 mV
VVBAT_OTGEN VBAT OTG enable rising threshold VSRN rising 3.25 3.55 3.85 V
VVBAT_OTGENZ VBAT OTG enable falling threshold VSRN falling 2.15 2.4 2.65 V
VVBAT_OTGEN_HYST VBAT OTG enable hysteresis 1150 mV
VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_UV VBUS undervoltage falling threshold As percentage of REG0x3B() 85%
tVBUS_OTG_UV VBUS time undervoltage deglitch 7 ms
VBUS OVER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_OV VBUS overvoltage rising threshold As percentage of REG0x3B() 110%
tVBUS_OTG_OV VBUS Time Overvoltage Deglitch 10 ms
PRE-CHARGE to FAST CHARGE TRANSITION(For ≥2S)
VBAT_VSYS_MIN_RISE LDO mode to fast charge mode threshold, VSRN rising as percentage of 0x3E() 98% 100% 102%
VBAT_VSYS_MIN_FALL LDO mode to fast charge mode threshold, VSRN falling as percentage of 0x3E() 97.5%
VBAT_VSYS_MIN_HYST Fast charge mode to LDO mode threshold hysteresis as percentage of 0x3E() 2.5%
BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Threshold for 1S)
VBATLV_FALL BATLOWV falling threshold 2.8 V
VBATLV_RISE BATLOWV rising threshold 3 V
VBATLV_RHYST BATLOWV hysteresis 200 mV
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV_RISE VBUS overvoltage rising threshold VBUS rising 26.0 26.8 27.7 V
VACOV_FALL VBUS overvoltage falling threshold VBUS falling 25.0 25.8 26.7 V
VACOV_HYST VBUS overvoltage hysteresis 1.0 V
tACOV_RISE_DEG VBUS deglitch overvoltage rising VBUS converter rising to stop converter 100 us
tACOV_FALL_DEG VBUS deglitch overvoltage falling VBUS converter falling to start converter 1 ms
INPUT OVER CURRENT COMPARATOR (ACOC)
VACOC ACP to ACN rising threshold, w.r.t. ILIM2 in REG0x33[15:11] Voltage across input sense resistor rising, Reg0x31[2]= 1 180% 200% 220%
VACOC_FLOOR Measure between ACP and ACN Set IIN_DPM to minimum 44 50 56 mV
VACOC_CEILING Measure between ACP and ACN Set IIN_DPM to maximum 172 180 188 mV
tACOC_DEG_RISE Rising deglitch time Deglitch time to trigger ACOC 250 us
tACOC_RELAX Relax time Relax time before converter starts again 250 ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
VSYSOVP_RISE System overvoltage rising threshold to turnoff converter 1 s 5.8 6 6.1 V
2 s 11.7 12 12.2 V
3 s 19 19.5 20 V
4 s 19 19.5 20 V
VSYSOVP_FALL System overvoltage falling threshold 1 s 5.5 V
2 s 11.7 V
3 s 19.3 V
4 s 19.3 V
ISYSOVP Discharge current when SYSOVP stop switching was triggered on VSYS pin 20 mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
VBATOVP_RISE Overvoltage rising threshold as percentage of VBAT_REG in REG0x15() 1 s, 4.2 V 102.5% 104% 106%
≥2 s 102.5% 104% 105%
VBATOVP_FALL Overvoltage falling threshold as percentage of VBAT_REG in REG0x15() 1 s 100% 102% 104%
≥2 s 100% 102% 103%
VBATOVP_HYST Overvoltage hysteresis as percentage of VBAT_REG in REG0x15() 1 s 2%
≥2 s 2%
IBATOVP Discharge current during BATOVP Discharge current through VSYS pin 40 mA
CONVERTER OVER-CURRENT COMPARATOR (Q2)
VOCP_limit_Q2 Converter Over-Current Limit across Q2 MOSFET drain to source voltage Reg0x31[5]=1 150 mV
Reg0x31[5]=0 210 mV
VOCP_limit_SYSSHORT_Q2 System Short or SRN < 2.4 V Reg0x31[5]=1 45 mV
Reg0x31[5]=0 60 mV
CONVERTER OVER-CURRENT COMPARATOR (ACX)
VOCP_limit_ACX Converter Over-Current Limit across ACP-ACN input current sensing resistor Reg0x31[4]=1; RSNS_RAC=0b 150 mV
Reg0x31[4]=0;RSNS_RAC=0b 280 mV
VOCP_limit_SYSSHORT_ACX System Short or SRN < 2.4 V Reg0x31[4]=1 90 mV
Reg0x31[4]=0 150 mV
THERMAL SHUTDOWN COMPARATOR
TSHUT_RISE Thermal shutdown rising temperature Temperature increasing 155 °C
TSHUTF_FALL Thermal shutdown falling temperature Temperature reducing 135 °C
TSHUT_HYS Thermal shutdown hysteresis 20 °C
tSHUT_RDEG Thermal deglitch shutdown rising 100 us
tSHUT_FHYS Thermal deglitch shutdown falling 12 ms
ICRIT PROCHOT COMPARATOR
IICRIT_PRO Input current rising threshold for throttling as 10% above ILIM2 (REG0x33[15:11]) Only when ILIM2 setting is higher than 2A 105% 110% 117%
INOM PROCHOT COMPARATOR
IINOM_PRO INOM rising threshold as 10% above IIN_DPM (REG0x22[15:8]) 105% 110% 116%
BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG)
IDCHG_TH1 IDCHG threshold1 for throttling CPU Reg0x34h<15:10>=010000b, with 10mΩ SRP/SRN current sensing resistor 8192 mA
96% 103%
IDCHG_DEG1 IDCHG threshold1 deglitch time Reg0x34h<9:8>=01b 1.25 sec
IDCHG_TH2 IDCHG threshold2 for throttling CPU Reg0x34h<15:10>=010000b 36h<5:3>=001b,with 10mΩ SRP/SRN current sensing resistor 12288 mA
96% 103%
tDCHG_DEG2 IDCHG threshold2 deglitch time Reg0x36h<7:6>=01b 1.6 ms
INDEPENDENT COMPARATOR
VINDEP_CMP Independent comparator threshold Reg0x30h<7>= 1, CMPIN falling 1.17 1.2 1.23 V
Reg0x30h<7>= 0, CMPIN falling 2.27 2.3 2.33 V
VINDEP_CMP_HYS Independent comparator hysteresis CMPIN falling 100 mV
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP
FSW PWM switching frequency Reg0x12[9] = 0 1020 1200 1380 kHz
FSW PWM switching frequency Reg0x12[9] = 1 680 800 920 kHz
BATFET GATE DRIVER (BATDRV)
VBATDRV_ON Gate drive voltage on BATFET 8.5 10 11.5 V
VBATDRV_DIODE Drain-source voltage on BATFET during ideal diode operation 30 mV
RBATDRV_ON Measured by sourcing 10 µA current to BATDRV 3 4 6 kΩ
RBATDRV_OFF Measured by sinking 10 µA current from BATDRV 1.2 2.1 kΩ
PWM HIGH SIDE DRIVER (HIDRV Q1)
RDS_HI_ON_Q1 High-side driver (HSD) turnon resistance VBTST1 - VSW1 = 5 V 6 Ω
RDS_HI_OFF_Q1 High-side driver turnoff resistance VBTST1 - VSW1 = 5 V 1.3 2.2 Ω
VBTST1_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST1 - VSW1 when low-side refresh pulse is requested 3.2 3.7 4.6 V
PWM HIGH SIDE DRIVER (HIDRV Q4)
RDS_HI_ON_Q4 High-side driver (HSD) turnon resistance VBTST2 - VSW2 = 5 V 6 Ω
RDS_HI_OFF_Q4 High-side driver turnoff resistance VBTST2 - VSW2 = 5 V 1.5 2.4 Ω
VBTST2_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST2 - VSW2 when low-side refresh pulse is requested 3.3 3.7 4.6 V
PWM LOW SIDE DRIVER (LODRV Q2)
RDS_LO_ON_Q2 Low-side driver (LSD) turnon resistance VBTST1 - VSW1 = 5.5 V 6 Ω
RDS_LO_OFF_Q2 Low-side driver turnoff resistance VBTST1 - VSW1 = 5.5 V 1.7 2.6 Ω
PWM LOW SIDE DRIVER (LODRV Q3)
RDS_LO_ON_Q3 Low-side driver (LSD) turnon resistance VBTST2 - VSW2 = 5.5 V 7.6 Ω
RDS_LO_OFF_Q3 Low-side driver turnoff resistance VBTST2 - VSW2 = 5.5 V 2.9 4.6 Ω
INTERNAL SOFT START During Charge Enable
SSSTEP_SIZE Charge current soft-start step size 64 mA
SSSTEP_TIME Charge current soft-start duration time for each step 8 us
INTEGRATED BTST DIODE (D1)
VF_D1 Forward bias voltage IF = 20 mA at 25°C 0.8 V
VR_D1 Reverse breakdown voltage IR = 2 µA at 25°C 20 V
INTEGRATED BTST DIODE (D2)
VF_D2 Forward bias voltage IF = 20 mA at 25°C 0.8 V
VR_D2 Reverse breakdown voltage IR = 2 µA at 25°C 20 V
INTERFACE
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold SMBus 0.8 V
VIN_ HI Input high threshold SMBus 2.1 V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
VOUT_ LO Output saturation voltage 5 mA drain current 0.4 V
VOUT_ LEAK Leakage current Voltage = 7 V –1 1 µA
LOGIC INPUT (OTG/VAP/FRS pin)
VIN_ LO_OTG Input low threshold 0.4 V
VIN_ HI_OTG Input high threshold 1.3 V
LOGIC OUTPUT OPEN DRAIN SDA
VOUT_ LO_SDA Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK_SDA Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
VOUT_ LO_CHRG_OK Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK _CHRG_OK Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN CMPOUT
VOUT_ LO_CMPOUT Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK _CMPOUT Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
VOUT_ LO_PROCHOT Output saturation voltage 50 Ω pullup to 1.05 V / 5-mA 300 mV
VOUT_ LEAK_PROCHOT Leakage current Voltage = 5.5 V –1 1 µA
ANALOG INPUT (ILIM_HIZ)
VHIZ_ LO Voltage to get out of HIZ mode ILIM_HIZ pin rising 0.8 V
VHIZ_ HIGH Voltage to enable HIZ mode ILIM_HIZ pin falling 0.4 V
ANALOG INPUT (CELL_BATPRESZ)
VCELL_4S 4S setting CELL_BATPRESZ pin voltage as percentage of REGN = 6 V 68.4% 75% 81.5%
VCELL_3S 3S setting CELL_BATPRESZ pin voltage as percentage of REGN = 6 V 51.7% 55% 65%
VCELL_2S 2S setting CELL_BATPRESZ pin voltage as percentage of REGN = 6 V 35% 40% 48.5%
VCELL_1S 1S setting CELL_BATPRESZ pin voltage as percentage of REGN = 6 V 18.4% 25% 31.6%
VCELL_BATPRESZ_RISE Battery is present CELL_BATPRESZ rising 18%
VCELL_BATPRESZ_FALL Battery is removed CELL_BATPRESZ falling 15%
ANALOG INPUT (COMP1, COMP2)
ILEAK_COMP1 COMP1 Leakage –120 120 nA
ILEAK_COMP2 COMP2 Leakage –120 120 nA