The BQ25720 device operates as a target, receives control inputs from the embedded controller host through the SMBus interface. The BQ25720 device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The device uses the SMBus read-word and write-word protocols (shown in Table 9-7 and Table 9-8) to communicate with the smart battery. The device performs only as a SMBus target device with address 0b0001001_X (0x12H Write/0x13H Read) and does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication starts when VBUS is above V_{VBUS_UVLO} or VBAT is above V_{VBAT_UVLO}.

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the host signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the host has finished communicating, the host issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 9-6 and Figure 9-7 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the device because either the host or the target acknowledges the receipt of the correct byte during the ninth clock cycle. The BQ25720 supports the charger commands listed in Table 9-7.