JAJSM47A May   2021  – November 2021 CC1352P7

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram – RGZ Package (Top View)
    2. 6.2 Signal Descriptions – RGZ Package
    3. 6.3 Connections for Unused Pins and Modules
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power Supply and Modules
    5. 7.5  Power Consumption - Power Modes
    6. 7.6  Power Consumption - Radio Modes
    7. 7.7  Nonvolatile (Flash) Memory Characteristics
    8. 7.8  Thermal Resistance Characteristics
    9. 7.9  RF Frequency Bands
    10. 7.10 861 MHz to 1054 MHz - Receive (RX)
    11. 7.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 7.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 7.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 7.14 Bluetooth Low Energy - Receive (RX)
    15. 7.15 Bluetooth Low Energy - Transmit (TX)
    16. 7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    17. 7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    18. 7.18 Timing and Switching Characteristics
      1. 7.18.1 Reset Timing
      2. 7.18.2 Wakeup Timing
      3. 7.18.3 Clock Specifications
        1. 7.18.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 7.18.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 7.18.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 7.18.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
        5. 7.18.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 7.18.4 Synchronous Serial Interface (SSI) Characteristics
        1. 7.18.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       40
      5. 7.18.5 UART
        1. 7.18.5.1 UART Characteristics
    19. 7.19 Peripheral Characteristics
      1. 7.19.1 ADC
        1. 7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 7.19.2 DAC
        1. 7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 7.19.3 Temperature and Battery Monitor
        1. 7.19.3.1 Temperature Sensor
        2. 7.19.3.2 Battery Monitor
      4. 7.19.4 Comparators
        1. 7.19.4.1 Low-Power Clocked Comparator
        2. 7.19.4.2 Continuous Time Comparator
      5. 7.19.5 Current Source
        1. 7.19.5.1 Programmable Current Source
      6. 7.19.6 GPIO
        1. 7.19.6.1 GPIO DC Characteristics
    20. 7.20 Typical Characteristics
      1. 7.20.1 MCU Current
      2. 7.20.2 RX Current
      3. 7.20.3 TX Current
      4. 7.20.4 RX Performance
      5. 7.20.5 TX Performance
      6. 7.20.6 ADC Performance
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Proprietary Radio Formats
      2. 8.3.2 Bluetooth 5.2 Low Energy
      3. 8.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN)
    4. 8.4  Memory
    5. 8.5  Sensor Controller
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Serial Peripherals and I/O
    9. 8.9  Battery and Temperature Monitor
    10. 8.10 µDMA
    11. 8.11 Debug
    12. 8.12 Power Management
    13. 8.13 Clock Systems
    14. 8.14 Network Processor
  9. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
    3. 10.3 Documentation Support
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics

Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers.
 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample Rate 200 ksps
Offset Internal 4.3 V equivalent reference(2) ±2 LSB
Gain error Internal 4.3 V equivalent reference(2) ±7 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL Integral nonlinearity ±4 LSB
ENOB Effective number of bits Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone 		9.8 Bits
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled 		9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 10.1
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone 		11.1
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 600 Hz input tone (5) 		11.3
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone (5) 		11.6
THD Total harmonic distortion Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 –65 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone –70
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 –72
SINAD,
SNDR		 Signal-to-noise
and
distortion ratio		 Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 60 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 68
SFDR Spurious-free dynamic range Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 70 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 75
Conversion time Serial conversion, time-to-output, 24 MHz clock 50 Clock Cycles
Current consumption Internal 4.3 V equivalent reference(2) 0.40 mA
Current consumption VDDS as reference 0.57 mA
Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1 4.3(2)(3) V
Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095		 1.48 V
Reference voltage VDDS as reference, input voltage scaling enabled VDDS V
Reference voltage VDDS as reference, input voltage scaling disabled VDDS / 2.82(3) V
Input impedance 200 kSamples/s, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time >1 MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings at all times
(4) No missing codes
(5) ADC_output = Σ(4n samples ) >> n, n = desired extra bits