JAJSM76E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

7.3.4 N Divider and Fractional Circuitry

The N divider (12 bits) includes a multi-stage noise shaping (MASH) sigma-delta modulator with programmable order from 1st to 4th order, which performs fractional compensation and can achieve any fractional denominator from 1 to (232 – 1). Using programmable registers, PLL_N is the integer portion and PLL_NUM / PLL_DEN is the fractional portion, thus the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows the output frequency to be a fractional multiplication of the phase detector frequency. The higher the denominator the finer the resolution step of the output. There is a N divider prescaler (PLL_N_PRE) between the VCO and the N divider which performs a division of 2 or 4. 2 is selected typically for higher performance in fractional mode and 4 may be desirable for lower power operation and when N is approaching max value.

Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)

Minimum output frequency step = Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]

Typically, higher modulator order pushes the noise out in frequency and may be filtered out with the PLL. However, several tradeoff needs to be made. Table 7-2 shows the suggested minimum N value while in fractional mode as a function of the sigma-delta modulator order. It also describe the recommended register setting for the PFD delay (register PFD_DLY_SEL).

Table 7-2 MASH Order and N Divider
INTEGER-N1st ORDER2nd ORDER3rd ORDER4th ORDER
Minimum N divider (low bound)911161830
PFD delay recommended setting (PFD_DLY_SEL)11228