JAJSMA3A December   2021  – September 2024 LP5866

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
      3. 7.3.3 PWM Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Recommendations
      2. 8.3.2 Power Supply Recommendations
      3. 8.3.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.3.1 Program Procedure

When selecting data refresh Mode 1, outputs are refreshed instantly after data is received.

When selecting data refresh Mode 2/3, VSYNC signal is required for synchronized display. Programming flow is shown as Figure 8-2. To display full pixel of last frame, VSYNC pulse must be sent to the device after the end of last PWM. Time between two pulses tSYNC must be larger than the whole PWM time of all Dots tframe. Common selection like 60Hz, 90Hz, 120Hz or even higher refresh frequency can be supported. High pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame, and data must not be write to PWM registers during high pulse width.

LP5866 Program ProcedureFigure 8-2 Program Procedure