JAJSMA3A December   2021  – September 2024 LP5866

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
      3. 7.3.3 PWM Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Recommendations
      2. 8.3.2 Power Supply Recommendations
      3. 8.3.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

LP5866 LP5866 RKP Package 40-Pin VQFN With Exposed Thermal Pad Top View Figure 5-1 LP5866 RKP Package 40-Pin VQFN With Exposed Thermal Pad Top View

LP5866

Figure 5-2 LP5866 DBT Package 38-Pin TSSOP Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME VQFN NO. TSSOP NO.
CS0 1 15 O Current sink 0. If not used, this pin must be left floating.
CS1 2 16 O Current sink 1. If not used, this pin must be left floating.
CS2 3 17 O Current sink 2. If not used, this pin must be left floating.
CS3 4 18 O Current sink 3. If not used, this pin must be left floating.
CS4 5 19 O Current sink 4. If not used, this pin must be left floating.
CS5 6 20 O Current sink 5. If not used, this pin must be left floating.
CS6 7 21 O Current sink 6. If not used, this pin must be left floating.
CS7 8 22 O Current sink 7. If not used, this pin must be left floating.
CS8 9 23 O Current sink 8. If not used, this pin must be left floating.
SW0 10 24 O High-side PMOS switch output for scan line 0. If not used, this pin must be left floating.
SW1 11 25 O High-side PMOS switch output for scan line 1. If not used, this pin must be left floating.
SW2 12 26 O High-side PMOS switch output for scan line 2. If not used, this pin must be left floating.
SW3 13 31 O High-side PMOS switch output for scan line 3. If not used, this pin must be left floating.
SW4 14 32 O High-side PMOS switch output for scan line 4. If not used, this pin must be left floating.
SW5 15 33 O High-side PMOS switch output for scan line 5. If not used, this pin must be left floating.
VLED 16 30 Power Power input for high-side switches
NC 17, 18, 19, 20, 21 27, 29 – No internal connection
CS9 22 34 O Current sink 9. If not used, this pin must be left floating.
CS10 23 35 O Current sink 10. If not used, this pin must be left floating.
CS11 24 36 O Current sink 11. If not used, this pin must be left floating.
CS12 25 37 O Current sink 12. If not used, this pin must be left floating.
CS13 26 38 O Current sink 13. If not used, this pin must be left floating.
CS14 27 1 O Current sink 14. If not used, this pin must be left floating.
CS15 28 2 O Current sink 15. If not used, this pin must be left floating.
CS16 29 3 O Current sink 16. If not used, this pin must be left floating.
CS17 30 4 O Current sink 17. If not used, this pin must be left floating.
AGND 31 5 Ground Analog ground. Must be connected to exposed thermal pad and common ground plane.
VCAP 32 6 O Internal LDO output. A 1-μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
IFS 33 7 I Interface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
VSYNC 34 8 I External synchronize signal for display mode 2 and mode 3
SCL_SCLK 35 9 I I2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
SDA_MOSI 36 10 I/O I2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
ADDR0_MISO 37 11 I/O I2C address select 0 or SPI leader input follower output
ADDR1_SS 38 12 I I2C address select 1 or SPI follower select
VIO_EN 39 13 Power,I Power supply for digital circuits and chip enable. A 1-nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
VCC 40 14 Power Power supply for device. A 1-μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
GND Exposed Thermal Pad / Ground Must be connected to AGND and common ground plane