JAJSMA3A December   2021  – September 2024 LP5866

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
      3. 7.3.3 PWM Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Recommendations
      2. 8.3.2 Power Supply Recommendations
      3. 8.3.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

VCC = 3.3 V, VLED = 3.8 V, VIO = 1.8 V and TA = –40 °C to +85 °C (TA = –55 °C to +125 °C for LP5866MDBT); Typical values are at TA = 25 °C (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power supplies
VCC Device supply voltage 2.7 5.5 V
VUVR Undervoltage restart VCC rising, Test mode 2.5 V
VUVF Undervoltage shutdown VCC falling, Test mode 1.9 V
VUV_HYS Undervoltage shutdown hysteresis 0.3 V
VCAP Internal LDO output VCC = 2.7 V to 5.5 V 1.78 V
ICC Shutdown supply current ISHUTDOWN VEN = 0 V, CHIP_EN = 0 (bit), measure the total current from VCC and VLED 0.1 1 µA
Standby supply current ISTANDBY VEN = 3.3 V, CHIP_EN = 0 (bit), measure the total current from VCC and VLED 5.5 10 µA
VEN = 3.3 V, CHIP_EN = 0 (bit), measure the total current from VCC and VLED, LP5866MDBT 5.5 15 µA
Active mode supply current INORMAL VEN = 3.3 V, CHIP_EN = 1 (bit), all channels IOUT = 5 mA (MC = 1, CC = 127, DC = 256), measure the current from VCC 4.3 6 mA
VLED LED supply voltage 2.7 5.5 V
VVIO VIO supply voltage 1.65 5.5 V
IVIO VIO supply current Interface idle 5 µA
Output Stages
ICS Constant current sink output range (CS0 – CS17) 2.7 <= VCC < 3.3 V, PWM = 100% 0.1 40 mA
VCC >= 3.3 V PWM = 100% 0.1 50 mA
ILKG Leakage current (CS0 – CS17) channels off, up_deghost = 0, VCS = 5 V 0.1 1 µA
IERR_DD Device to device current error, IERR_DD = (IAVE - ISET) / ISET × 100% All channels ON. Current set to 0.1 mA. MC = 0 CC = 42 DC = 25 PWM = 100% –7 7 %
All channels ON. Current set to 1 mA. MC = 2 CC = 127 DC = 25 PWM = 100% –5 5 %
All channels ON. Current set to 10 mA. MC = 2 CC = 127 DC = 255 PWM = 100% –3.5 3.5 %
All channels ON. Current set to 25 mA. MC = 7 CC = 64 DC = 255 PWM = 100% –3.5 3.5 %
All channels ON. Current set to 50 mA. MC = 7 CC = 127 DC = 255 PWM = 100% –3 3 %
IERR_CC Channel to channel current error, IERR_CC = (IOUTX - IAVE) / IAVE × 100% All channels ON. Current set to 0.1 mA. MC = 0 CC = 42 DC = 25 PWM = 100% –5.5 5.5 %
All channels ON. Current set to 1 mA. MC = 2 CC = 127 DC = 25 PWM = 100% –5 5 %
All channels ON. Current set to 10 mA. MC = 2 CC = 127 DC = 255 PWM = 100% –4 4 %
All channels ON. Current set to 25 mA. MC = 7 CC = 64 DC = 255 PWM = 100% –3.5 3.5 %
All channels ON. Current set to 50 mA. MC = 7 CC = 127 DC = 255 PWM = 100% –3 3 %
fPWM LED PWM frequency PWM_Fre = 1, PWM = 100% 62.5 KHz
PWM_Fre = 0, PWM = 100% 125 KHz
VSAT Output saturation voltage IOUT = 50 mA, decreasing output voltage, when the LED current has dropped 5% 0.45 V
IOUT = 30 mA, decreasing output voltage, when the LED current has dropped 5% 0.4 V
IOUT = 10 mA, decreasing output voltage, when the LED current has dropped 5% 0.35 V
RSW High-side PMOS ON resistance VLED = 2.7 V, ISW = 200 mA 450 mΩ
VLED = 3.8 V, ISW = 200 mA 380 mΩ
VLED = 5 V, ISW = 200 mA 310 mΩ
Logic Interfaces
VLOGIC_IL Low-level input voltage, SDA, SCL, SCLK, MOSI, SS, ADDRx, VSYNC, IFS 0.3 × VIO V
VLOGIC_IH High-level input voltage, SDA, SCL, SCLK, MOSI, SS, ADDRx, VSYNC, IFS 0.7 × VIO V
VEN_IL Low-level input voltage of EN 0.4 V
VEN_IH High-level input voltage of EN When VCAP powered up 1.4 V
ILOGIC_I Input current, SDA, SCL, SCLK, MOSI, SS, ADDRx –1 1 µA
VLOGIC_OL Low-level output voltage, SDA, MISO IPULLUP = 3 mA 0.4 V
VLOGIC_OH High-level output voltage, MISO IPULLUP = –3 mA 0.7 × VIO V
Protection Circuits
VLOD_TH Thershold for channel open detection 0.25 V
VLSD_TH Thershold for channel short detection VLED – 1 V
TTSD Thermal-shutdown junction temperature 150 °C
THYS Thermal shutdown temperature hysteresis 15 °C