JAJSMC5A June   2020  – August 2024 CD54HCT125 , CD74HCT125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT
25°C –40°C to 85°C –55°C to 125°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VOH  High-level output voltage VI = VIH or VIL IOH = –20 µA 4.5 V 4.4 4.4 4.4 V
IOH = –4 mA 4.5 V 3.98 3.84 3.7
VOL  Low-level output voltage VI = VIH or VIL IOL = 20 µA 4.5 V 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.26 0.33 0.4
II Input leakage current VI = VCC and GND IO = 0 5.5 V ±0.1 ±1 ±1 µA
IOZ Three-state leakage current VI = VIH or VIL 5.5 V ±0.5 ±5 ±10 µA
ICC Supply current VI = VCC or GND IO = 0
5.5 V

 8 80 160 µA
ΔICC(1) Additional Quiescent Device Current Per Input Pin. VI = VCC – 2.1 4.5 V to 5.5 V 100 360 450 490 µA
Ci Input capacitance 10 10 10 pF
Co Three-state output capacitance 20 20 20 pF
(1) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.