JAJSMP8C May   2023  – June 2024 OPT4001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Spectral Matching to Human Eye
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Error Correction Code (ECC) Features
        1. 6.3.3.1 Output Sample Counter
        2. 6.3.3.2 Output CRC
      4. 6.3.4 Output Register FIFO
      5. 6.3.5 Threshold Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
      2. 6.4.2 Interrupt Modes of Operation
      3. 6.4.3 Light Range Selection
      4. 6.4.4 Selecting Conversion Time
      5. 6.4.5 Light Measurement in Lux
      6. 6.4.6 Threshold Detection Calculations
      7. 6.4.7 Light Resolution
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Overview
        1. 6.5.1.1 Serial Bus Address
        2. 6.5.1.2 Serial Interface
      2. 6.5.2 Writing and Reading
        1. 6.5.2.1 High-Speed I2C Mode
        2. 6.5.2.2 Burst Read Mode
        3. 6.5.2.3 General-Call Reset Command
        4. 6.5.2.4 SMBus Alert Response (USON Variant)
  8. 7 Register Maps
    1. 7.1 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Electrical Interface
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Optical Interface
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Optomechanical Design (PicoStar Variant)
          2. 8.2.1.2.2 Optomechanical Design (USON Variant)
        3. 8.2.1.3 Application Curves (PicoStar Variant)
        4. 8.2.1.4 Application Curves (USON Variant)
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Soldering and Handling Recommendations (PicoStar Variant)
          1. 8.5.1.1.1 Solder Paste
          2. 8.5.1.1.2 Package Placement
          3. 8.5.1.1.3 Reflow Profile
          4. 8.5.1.1.4 Special Flexible Printed-Circuit Board (FPCB) Recommendations
          5. 8.5.1.1.5 Rework Process
        2. 8.5.1.2 Soldering and Handling Recommendations (USON Variant)
      2. 8.5.2 Layout Example
  10. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.4 Output Register FIFO

Output registers always contain the most recent light measurement. Along with the output registers, there are three more shadow registers that have data from the previous three measurements. For every new measurement, the data on the three shadow registers are updated to contain the most recent measurements, discarding the oldest measurement similar to a FIFO scheme. These shadow registers, along with the output registers, act like a FIFO with a depth of 4. The INT pin can be configured (as shown in Figure 6-2) to generate an interrupt for every measurement, or can be configured to generate an interrupt every four measurements using the INT_CFG register. In this manner, the controller reading data from the OPT4001-Q1 minimizes the number of interrupts by a factor of 4 and is still provided access to all four measurements between the interrupts. By using burst read mode, the output and FIFO registers can be read out with minimal I2C clocks.

OPT4001-Q1 FIFO Registers Data Movement Figure 6-2 FIFO Registers Data Movement