The device has two calibration modes available: foreground calibration and background calibration. When foreground calibration is initiated the ADCs are taken offline to calibrate and the output data becomes mid-code (0x000 in 2's complement) until calibration is finished. Background calibration allows the ADC to continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC core to take its place. Additional offset calibration features are available in both foreground and background calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user system.

The device consists of a total of six ADC cores. In foreground calibration mode ADC 0 samples INA±, ADC 1 samples INB±, ADC 4 samples INC± and ADC 5 samples IND±. In the background calibration modes, ADC core 2 is swapped in periodically for ADC 0 and ADC 1 and ADC core 3 is swapped in periodically for ADC 4 and 5 so that they can be calibrated without disrupting operation. Figure 6-15 through Figure 6-17 provide a diagrams of the calibration system including labeling of the ADC cores. When calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally generated calibration signal. The analog inputs can be driven during calibration, both foreground and background, except that when offset calibration (OS_CAL or BGOS_CAL) is used there must be no signals (or aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section).

Figure 6-15 Quad Channel Calibration System Block Diagram

Figure 6-16 DualChannel Calibration System Block Diagram

Figure 6-17 Single Channel Calibration System Block Diagram

In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal performance. These parameters include input offset voltage, ADC gain and input termination resistance. The default trim values are programmed at the factory to unique values for each device that are determined to be optimal at the test system operating conditions. The user can read the factory-programmed values from the trim registers and adjust as desired. The register fields that control the trimming are labeled according to the input that is being sampled (INA±, INB±, INC± or IND±) and the ADC core that is being trimmed. The user is not expected to change the trim values as operating conditions change, however the user can change values as needed. Any custom trimming must be done on a per device basis because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming section for information about the available trim parameters and associated registers.