PD pin provides a 50-µA drive and 88-mA peak pulldown strength for the load disconnect switch stage. Connect the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.

For inrush current limiting, connect C_dVdT capacitor and R₁ as shown in Figure 8-2.

The C_dVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current limiting. Use Equation 1 to calculate C_dVdT capacitance value.

where I_{PD_DRV} is 50 μA (typical), I_INRUSH is the inrush current, and C_OUT is the output load capacitance. An extra resistor, R₁, in series with the C_dVdT capacitor improves the turn-off time.

PD is pulled low during the following conditions:

• During an OV event with the OV pin voltage rising above the V_(OVR) threshold

• When the EN pin is pulled low with V_(EN) driven lower than V_{(EN_IL)} level

• When the voltage at VS pin drops below the V_{(VS POR)} falling threshold

During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the external Zener (Dz).

The peak power dissipated in the LM74720-Q1 at the instance of PD pulldown can be calculated approximately using Equation 2.

where

• I_{PDSINK_peak} is the peak sink current of 88 mA (typical)

In the system designs with input voltage above 48 V, TI recommends to place a resistor, R_PD, in series with the PD pin as shown in Figure 8-2. The peak power dissipation during the pulldown events gets distributed in RPD and the internal PD switch. A resistor value in the range of 270 Ω to 330 Ω can be selected to limit the device power dissipation within the safe limits. Figure 6-12 shows the turn-OFF delay characteristics with various resistors.