JAJSN29B october   2021  – march 2023 TMUX8211 , TMUX8212 , TMUX8213

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings: TMUX821x Devices
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: TMUX821x Devices
    4. 7.4  ソースまたはドレイン連続電流
    5. 7.5  ドレイン・パルス電流のソース
    6. 7.6  Thermal Information
    7. 7.7  Electrical Characteristics (Global): TMUX821x Devices
    8. 7.8  Electrical Characteristics (±15-V Dual Supply)
    9. 7.9  Electrical Characteristics (±36-V Dual Supply)
    10. 7.10 Electrical Characteristics (±50-V Dual Supply)
    11. 7.11 Electrical Characteristics (72-V Single Supply)
    12. 7.12 Electrical Characteristics (100-V Single Supply)
    13. 7.13 Switching Characteristics: TMUX821x Devices
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 On-Resistance
    2. 8.2 Off-Leakage Current
    3. 8.3 On-Leakage Current
    4. 8.4 Device Turn-On and Turn-Off Time
    5. 8.5 Charge Injection
    6. 8.6 Off Isolation
    7. 8.7 Crosstalk
    8. 8.8 Bandwidth
    9. 8.9 THD + Noise
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Flat On-Resistance
      3. 9.3.3 Protection Features
        1. 9.3.3.1 Fail-Safe Logic
        2. 9.3.3.2 ESD Protection
        3. 9.3.3.3 Latch-Up Immunity
      4. 9.3.4 1.8 V Logic Compatible Inputs
      5. 9.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

GUID-20201103-CA0I-468W-CFHG-CXKG6TZT5RFB-low.svgFigure 6-1 PW Package, 16-Pin TSSOP (Top View)
GUID-20201103-CA0I-FHHJ-PDB0-9QFHLXCPB42J-low.svgFigure 6-2 RUM Package, 16-Pin WQFN (Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
D1 2 16 I/O Drain pin 1. Can be an input or output.
D2 15 13 I/O Drain pin 2. Can be an input or output.
D3 10 8 I/O Drain pin 3. Can be an input or output.
D4 7 5 I/O Drain pin 4. Can be an input or output.
GND 5 3 P Ground (0 V) reference
S1 1 15 I/O Source pin 1. Can be an input or output.
S2 16 14 I/O Source pin 2. Can be an input or output.
S3 9 7 I/O Source pin 3. Can be an input or output.
S3 9 7 I/O Source pin 3. Can be an input or output.
S4 8 6 I/O Source pin 4. Can be an input or output.
SEL1 3 2 I Logic control input 1.
SEL2 14 12 I Logic control input 2.
SEL3 11 11 I Logic control input 3.
SEL4 6 4 I Logic control input 4.
N.C. 12 10 — No internal connection.
VDD 13 9 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 1 µF to 10 µF between VDD and GND.
VSS 4 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 1 µF to 10 µF between VSS and GND.
Thermal Pad — The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power