JAJSN97D
November 2021 – August 2023
TPSI3050-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristic Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Transmission of the Enable State
8.3.2
Power Transmission
8.3.3
Gate Driver
8.3.4
Modes Overview
8.3.5
Three-Wire Mode
8.3.6
Two-Wire Mode
8.3.7
VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
8.3.8
Power Supply and EN Sequencing
8.3.9
Thermal Shutdown
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Two-Wire or Three-Wire Mode Selection
9.2.2.2
Standard Enable, One-Shot Enable
9.2.2.3
CDIV1, CDIV2 Capacitance
9.2.2.4
RPXFR Selection
9.2.2.5
CVDDP Capacitance
9.2.2.6
Gate Driver Output Resistor
9.2.2.7
Start-up Time and Recovery Time
9.2.2.8
Supplying Auxiliary Current, IAUX From VDDM
9.2.2.9
VDDM Ripple Voltage
9.2.3
Application Curves
9.2.4
Insulation Lifetime
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Related Links
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Mechanical, Packaging, and Orderable Information
8.2
Functional Block Diagram