JAJSNB2D November   2021  – September 2024 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configurations and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions - Digital
    4. 5.4 Signal Descriptions - Analog
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.5.2 Hardware Requirements
      3. 6.5.3 Impact to Your Hardware Warranty
    6. 6.6  Power Supply Specifications
    7. 6.7  Power Consumption Summary
    8. 6.8  RF Specifications
    9. 6.9  Thermal Resistance Characteristics
    10. 6.10 Power Supply Sequencing and Reset Timing
    11. 6.11 Input Clocks and Oscillators
      1. 6.11.1 Clock Specifications
    12. 6.12 Peripheral Information
      1. 6.12.1  QSPI Flash Memory Peripheral
        1. 6.12.1.1 QSPI Timing Conditions
        2. 6.12.1.2 QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 6.12.1.3 QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
      2. 6.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.12.2.1 MibSPI Peripheral Description
        2. 6.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 6.12.2.2.1 SPI Timing Conditions
          2. 6.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
          3. 6.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
        3. 6.12.2.3 SPI Peripheral Mode I/O Timings
          1. 6.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
      3. 6.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 6.12.3.1  RGMII Timing Conditions
        2. 6.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 6.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 6.12.3.4  RGMII Receive Clock Timing Requirements
        5. 6.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 6.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 6.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 6.12.3.8  RMII Receive Clock Timing Requirements
        9. 6.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 6.12.3.10 MII Transmit Switching Characteristics
        11. 6.12.3.11 MII Receive Clock Timing Requirements
        12. 6.12.3.12 MII Receive Timing Requirements
        13. 6.12.3.13 MII Transmit Clock Timing Requirements
        14. 6.12.3.14 MDIO Interface Timings
      4. 6.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 6.12.4.1 LVDS Interface Configuration
        2. 6.12.4.2 LVDS Interface Timings
      5. 6.12.5  UART Peripheral
        1. 6.12.5.1 SCI Timing Requirements
      6. 6.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 6.12.6.1 I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
      7. 6.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 6.12.8  CSI2 Receiver Peripheral
        1. 6.12.8.1 CSI2 Switching Characteristics
      9. 6.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 6.12.10 General-Purpose Input/Output
        1. 6.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
    13. 6.13 Emulation and Debug
      1. 6.13.1 Emulation and Debug Description
      2. 6.13.2 JTAG Interface
        1. 6.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 6.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 6.13.3 ETM Trace Interface
        1. 6.13.3.1 ETM TRACE Timing Requirements
        2. 6.13.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 RF Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interfaces
    4. 7.4 Other Subsystems
      1. 7.4.1 Hardware Accelerator Subsystem
      2. 7.4.2 Security – Hardware Security Module
      3. 7.4.3 ADC Channels (Service) for User Application
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Short and Medium Range Radar
    3. 9.3 Reference Schematic
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 Device Support
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation support
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 ドキュメントの更新通知を受け取る方法
    8. 10.8 静電気放電に関する注意事項
    9. 10.9 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.2 Pin Attributes

BALL NUMBER (1) PAD NAME (9) BALL NAME (2) SIGNAL NAME (3) MODE (4),(8) TYPE (5) BALL RESET STATE (6) PULL UP/DOWN TYPE (7)
V16 PAD_AA MSS_MIBSPIB_CS1 MSS_GPIO_12 0 IO Output Disabled Pull Down
MSS_MIBSPIA_HOSTIRQ 1 O
ADC_VALID 2 O
MSS_MIBSPIB_CS1 6 IO
B15 PAD_AB MSS_GPIO_0 MSS_GPIO_13 0 IO Output Disabled Pull Down
MSS_GPIO_0 1 IO
PMIC_CLKOUT 2 O
MSS_EPWM_TZ2 3 I
MSS_EPWMA1 10 O
MSS_EPWMB0 11 O
A16 PAD_AC MSS_GPIO_1 MSS_GPIO_16 0 IO Output Disabled Pull Down
MSS_GPIO_1 1 IO
SYNC_OUT 2 O
MSS_EPWM_TZ1 3 I
BSS_UARTA_TX 7 O
READY_INT 8 O
LVDS_VALID 9 O
DMM_MUX_IN 12 I
MSS_MIBSPIB_CS1 13 IO
MSS_MIBSPIB_CS2 14 IO
MSS_EPWMA_SYNCI 15 I
V12 PAD_AH MSS_MIBSPIB_MOSI MSS_GPIO_21 0 IO Output Disabled Pull Up
MSS_MIBSPIB_MOSI 1 IO
MSS_I2CA_SDA 2 IO
MSS_EPWMA0 3 O
MSS_MCANB_RX 7 I
U13 PAD_AI MSS_MIBSPIB_MISO MSS_GPIO_22 0 IO Output Disabled Pull Up
MSS_MIBSPIB_MISO 1 IO
MSS_I2CA_SCL 2 IO
MSS_EPWMB0 3 O
DSS_UARTA_TX 6 IO
MSS_MCANB_TX 7 O
T13 PAD_AJ MSS_MIBSPIB_CLK MSS_GPIO_5 0 IO Output Disabled Pull Up
MSS_MIBSPIB_CLK 1 IO
MSS_UARTA_RX 2 IO
MSS_EPWMC0 3 O
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
MSS_MCANA_RX 8 I
U14 PAD_AK MSS_MIBSPIB_CS0 MSS_GPIO_4 0 IO Output Disabled Pull Up
MSS_MIBSPIB_CS0 1 IO
MSS_UARTA_TX 2 IO
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
MSS_MCANA_TX 9 O
U11 PAD_AL MSS_QSPI_0 MSS_GPIO_8 0 IO Output Disabled Pull Down
MSS_QSPI_0 1 IO
MSS_MIBSPIB_MISO 2 IO
V11 PAD_AM MSS_QSPI_1 MSS_GPIO_9 0 IO Output Disabled Pull Down
MSS_QSPI_1 1 I
MSS_MIBSPIB_MOSI 2 IO
MSS_MIBSPIB_CS2 8 IO
T11 PAD_AN MSS_QSPI_2 MSS_GPIO_10 0 IO Output Disabled Pull Up
MSS_QSPI_2 1 I
ADC_VALID 2 O
MSS_MCANA_TX 8 O
R12 PAD_AO MSS_QSPI_3 MSS_GPIO_11 0 IO Output Disabled Pull Up
MSS_QSPI_3 1 I
ADC_VALID 2 O
MSS_MCANA_RX 8 I
R10 PAD_AP MSS_QSPI_CLK MSS_GPIO_7 0 IO Output Disabled Pull Down
MSS_QSPI_CLK 1 IO
MSS_MIBSPIB_CLK 2 IO
DSS_UARTA_TX 6 IO
U12 PAD_AQ MSS_QSPI_CS MSS_GPIO_6 0 IO Output Disabled Pull Up
MSS_QSPI_CS 1 O
MSS_MIBSPIB_CS0 2 IO
B12 PAD_AS WARM_RESET WARM_RESET 0 IO HiZ Input (Open drain)
C11 PAD_AT NERROR_OUT NERROR_OUT 0 O HiZ (Open drain)
C12 PAD_AU TCK MSS_GPIO_17 0 IO Output Disabled Pull Down
TCK 1 I
MSS_UARTB_TX 2 IO
BSS_UARTA_RX 6 I
MSS_MCANA_TX 8 O
C14 PAD_AV TMS MSS_GPIO_18 0 IO Output Disabled Pull Up
TMS 1 IO
BSS_UARTA_TX 2 O
MSS_MCANA_RX 6 I
D13 PAD_AW TDI MSS_GPIO_23 0 IO Output Disabled Pull Up
TDI 1 I
MSS_UARTA_RX 2 IO
DSS_UARTA_RX 7 IO
D15 PAD_AX TDO SOP[0] During Power-up I Output Enabled
MSS_GPIO_24 0 IO
TDO 1 O
MSS_UARTA_TX 2 IO
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
NDMM_EN 9 O
R15 PAD_AY MCU_CLKOUT MSS_GPIO_25 0 IO Output Disabled Pull Down
MCU_CLKOUT 1 O
TRACE_CLK 2 O
FRAME_START 7 O
READY_INT 8 O
LVDS_VALID 9 O
BSS_UARTA_RX 10 I
MSS_EPWMA0 12 O
DMM_CLK 14 I
OBS_CLKOUT 15 O
G15 PAD_AZ MSS_GPIO_2 MSS_GPIO_26 0 IO Output Disabled Pull Down
MSS_GPIO_2 1 IO
MSS_UARTB_TX 7 IO
MSS_GPIO_2 1 IO
SYNC_OUT 9 O
PMIC_CLKOUT 10 O
CHIRP_START 11 O
CHIRP_END 12 O
FRAME_START 13 O
MSS_EPWM_TZ0 14 I
LVDS_VALID 15 O
T17 PAD_BA PMIC_CLKOUT SOP[2] During Power-up I Output Disabled No Pull
MSS_GPIO_27 0 IO
PMIC_CLKOUT 1 O
OBS_CLKOUT 2 O
TRACE_CTL 3 O
CHIRP_START 6 O
CHIRP_END 7 O
FRAME_START 8 O
READY_INT 9 O
LVDS_VALID 10 O
MSS_EPWMA1 11 O
MSS_EPWMB0 12 O
DMM_SYNC 13 I
R17 PAD_BB MSS_GPIO_28 MSS_GPIO_28 0 IO Output Disabled Pull Down
SYNC_IN 1 I
ADC_VALID 2 O
MSS_UARTB_RX 6 IO
DMM_MUX_IN 7 I
DSS_UARTA_RX 8 IO
SYNC_OUT 9 O
R14 PAD_BC MSS_MIBSPIB_CS2 SOP[1] During Power-up I Output Disabled
MSS_GPIO_29 0 IO
SYNC_OUT 1 O
RCOSC_CLK 2 O
READY_INT 6 O
LVDS_VALID 7 O
DMM_MUX_IN 9 I
MSS_MIBSPIB_CS1 10 IO
MSS_MIBSPIB_CS2 11 IO
MSS_EPWMB0 12 O
MSS_EPWMB1 13 O
F16 PAD_BD MSS_RS232_RX MSS_GPIO_15 0 IO Output Disabled Pull Up
MSS_RS232_RX 1 IO
MSS_UARTA_RX 2 IO
TRACE_CLK 3 O
BSS_UARTA_TX 6 O
MSS_UARTB_RX 7 IO
MSS_MCANA_RX 8 I
MSS_I2CA_SCL 9 IO
MSS_EPWMB0 10 O
MSS_EPWMB1 11 O
MSS_EPWMC0 12 O
E17 PAD_BE MSS_RS232_TX MSS_GPIO_14 0 IO Output Enabled Pull Up
MSS_RS232_TX 1 IO
TRACE_CTL 2 O
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
READY_INT 8 O
LVDS_VALID 9 O
MSS_MCANA_TX 10 O
MSS_I2CA_SDA 11 IO
MSS_EPWMA0 12 O
MSS_EPWMA1 13 O
NDMM_EN 14 O
MSS_EPWMB0 15 O
U17 PAD_BF MSS_GPIO_31 TRACE_DATA_0 0 O Output Disabled Pull Down
MSS_GPIO_31 1 IO
DMM0 2 I
MSS_UARTA_TX 4 IO
MSS_I2CA_SDA 10 IO
P17 PAD_BG MSS_GPIO_30 TRACE_DATA_1 0 O Output Disabled Pull Down
MSS_GPIO_30 1 IO
DMM1 2 I
MSS_EPWMC_SYNCI 3 I
MSS_UARTA_RX 4 IO
MSS_GPIO_0 6 IO
MSS_I2CA_SCL 10 IO
T18 PAD_BH MSS_GPIO_8 TRACE_DATA_2 0 O Output Disabled Pull Down
MSS_GPIO_29 1 IO
DMM2 2 I
MSS_EPWMB_SYNCI 3 I
MSS_GPIO_1 6 IO
MSS_GPIO_8 7 IO
N15 PAD_BI MSS_GPIO_9 TRACE_DATA_3 0 O Output Disabled Pull Down
MSS_GPIO_28 1 IO
DMM3 2 I
MSS_EPWMC_SYNCO 4 O
MSS_GPIO_2 6 IO
MSS_GPIO_9 7 IO
P16 PAD_BJ MSS_GPIO_3 TRACE_DATA_4 0 O Output Disabled Pull Down
MSS_GPIO_3 1 IO
DMM4 2 I
MSS_EPWMB_SYNCO 4 O
MSS_GPIO_27 6 IO
L15 PAD_BK MSS_GPIO_4 TRACE_DATA_5 0 O Output Disabled Pull Down
MSS_GPIO_4 1 IO
DMM5 2 I
MSS_EPWM_TZ2 4 I
MSS_UARTB_TX 5 IO
MSS_GPIO_26 6 IO
M16 PAD_BL BSS_UARTA_TX TRACE_DATA_6 0 O Output Disabled Pull Down
MSS_GPIO_5 1 IO
DMM6 2 I
MSS_EPWM_TZ1 4 I
BSS_UARTA_TX 5 O
MSS_GPIO_25 6 IO
MSS_GPIO_10 7 IO
J15 PAD_BM MSS_GPIO_11 TRACE_DATA_7 0 O Output Disabled Pull Down
MSS_GPIO_6 1 IO
DMM7 2 I
MSS_EPWM_TZ0 4 I
DSS_UARTA_TX 5 IO
MSS_GPIO_24 6 IO
MSS_GPIO_11 7 IO
D17 PAD_BN MSS_MCANA_TX TRACE_DATA_8 0 O Output Disabled Pull Down
MSS_GPIO_7 1 IO
DMM8 2 I
MSS_MCANA_TX 4 O
MSS_EPWMA_SYNCI 5 I
MSS_GPIO_23 6 IO
D16 PAD_BO MSS_MCANA_RX TRACE_DATA_9 0 O Output Disabled Pull Down
MSS_GPIO_8 1 IO
DMM9 2 I
MSS_MCANA_RX 4 I
MSS_EPWMA_SYNCO 5 O
MSS_GPIO_22 6 IO
E15 PAD_BP MSS_EPWMA0 TRACE_DATA_10 0 O Output Disabled Pull Down
MSS_GPIO_9 1 IO
DMM10 2 I
MSS_EPWMA0 3 O
MSS_EPWMC0 4 O
MSS_GPIO_21 6 IO
C18 PAD_BQ MSS_EPWMA1 TRACE_DATA_11 0 O Output Disabled Pull Down
MSS_GPIO_10 1 IO
DMM11 2 I
MSS_EPWMA1 3 O
MSS_EPWMC1 4 O
MSS_GPIO_20 6 IO
B17 PAD_BR MSS_MCANB_TX TRACE_DATA_12 0 O Output Disabled Pull Down
MSS_GPIO_11 1 IO
DMM12 2 I
MSS_EPWMB0 3 O
MSS_EPWMA0 4 O
MSS_MCANB_TX 5 O
MSS_GPIO_19 6 IO
A17 PAD_BS MSS_MCANB_RX TRACE_DATA_13 0 O Output Disabled Pull Down
MSS_GPIO_12 1 IO
DMM13 2 I
MSS_EPWMB1 3 O
MSS_EPWMA1 4 O
MSS_MCANB_RX 5 I
MSS_GPIO_18 6 IO
C17 PAD_BT MSS_EPWMB0 TRACE_DATA_14 0 O Output Disabled Pull Down
MSS_GPIO_13 1 IO
DMM14 2 I
MSS_EPWMC0 3 O
MSS_EPWMB0 4 O
MSS_GPIO_17 6 IO
U8 PAD_BX MSS_GPIO_17 MSS_GPIO_17 0 IO Output Disabled Pull Down
MSS_MII_COL 1 I
MSS_RMII_REFCLK 2 IO
MSS_EPWMA1 6 O
R8 PAD_BY MSS_I2CA_SDA MSS_GPIO_18 0 IO Output Disabled HiZ (Open drain)
MSS_MII_CRS 1 I
MSS_RMII_CRS_DV 2 I
MSS_I2CA_SDA 3 IO
MSS_EPWMB1 6 O
U9 PAD_BZ MSS_I2CA_SCL MSS_GPIO_19 0 IO Output Disabled HiZ (Open drain)
MSS_MII_RXER 1 I
MSS_RMII_RXER 2 I
MSS_I2CA_SCL 3 IO
MSS_EPWMC1 6 O
R6 PAD_CA MSS_RGMII_TCTL MSS_GPIO_20 0 IO Output Disabled Pull Down
MSS_MII_TXEN 1 O
MSS_RMII_TXEN 2 O
MSS_RGMII_TCTL 3 O
MSS_EPWMA0 6 O
T7 PAD_CB MSS_RGMII_RCTL MSS_GPIO_21 0 IO Output Disabled
MSS_MII_RXDV 1 I
MSS_RGMII_RCTL 3 I
MSS_RMII_CRS_DV 4 I
MSS_UARTB_RX 5 IO
MSS_EPWMB0 6 O
U4 PAD_CC MSS_RGMII_TD3 MSS_GPIO_22 0 IO Output Disabled Pull Down
MSS_MII_TXD3 1 O
MSS_RGMII_TD3 3 O
MSS_UARTB_TX 5 IO
MSS_EPWMC0 6 O
U6 PAD_CD MSS_RGMII_TD2 MSS_GPIO_23 0 IO Output Disabled Pull Down
MSS_MII_TXD2 1 O
MSS_RGMII_TD2 3 O
U5 PAD_CE MSS_RGMII_TD1 MSS_GPIO_24 0 IO Output Disabled Pull Down
MSS_MII_TXD1 1 O
MSS_RMII_TXD1 2 O
MSS_RGMII_TD1 3 O
U7 PAD_CF MSS_RGMII_TD0 MSS_GPIO_25 0 IO Output Disabled Pull Down
MSS_MII_TXD0 1 O
MSS_RMII_TXD0 2 O
MSS_RGMII_TD0 3 O
V3 PAD_CG MSS_RGMII_TCLK MSS_GPIO_26 0 IO Output Disabled Pull Down
MSS_MII_TXCLK 1 I
MSS_RGMII_TCLK 3 O
T9 PAD_CH MSS_RGMII_RCLK MSS_GPIO_27 0 IO Output Disabled Pull Down
MSS_MII_RXCLK 1 I
MSS_RGMII_RCLK 3 I
MSS_RMII_REFCLK 4 IO
U10 PAD_CI MSS_RGMII_RD3 MSS_GPIO_28 0 IO Output Disabled
MSS_MII_RXD3 1 I
MSS_RGMII_RD3 3 I
V5 PAD_CJ MSS_RGMII_RD2 MSS_GPIO_29 0 IO Output Disabled
MSS_MII_RXD2 1 I
MSS_RGMII_RD2 3 I
V4 PAD_CK MSS_RGMII_RD1 MSS_GPIO_30 0 IO Output Disabled
MSS_MII_RXD1 1 I
MSS_RMII_RXD1 2 I
MSS_RGMII_RD1 3 I
V6 PAD_CL MSS_RGMII_RD0 MSS_GPIO_31 0 IO Output Disabled
MSS_MII_RXD0 1 I
MSS_RMII_RXD0 2 I
MSS_RGMII_RD0 3 I
T5 PAD_CM MSS_MDIO_DATA MSS_GPIO_30 0 IO Output Disabled Pull Up
MSS_MDIO_DATA 1 IO
R4 PAD_CN MSS_MDIO_CLK MSS_GPIO_31 0 IO Output Disabled Pull Up
MSS_MDIO_CLK 1 O
U15 PAD_CO MSS_MIBSPIA_MOSI MSS_GPIO_0 0 IO Output Disabled Pull Up
MSS_MIBSPIA_MOSI 5 IO
U16 PAD_CP MSS_MIBSPIA_MISO MSS_GPIO_1 0 IO Output Disabled Pull Up
MSS_MIBSPIA_MISO 5 IO
T16 PAD_CQ MSS_MIBSPIA_CLK MSS_GPIO_2 0 IO Output Disabled Pull Up
MSS_MIBSPIA_CLK 5 IO
T15 PAD_CR MSS_MIBSPIA_CS0 MSS_GPIO_3 0 IO Output Disabled Pull Up
MSS_MIBSPIA_CS0 5 IO
V17 PAD_CS MSS_MIBSPIA_HOSTIRQ MSS_GPIO_4 0 IO Output Disabled Pull Down
MSS_GPIO_2 2 IO
MSS_GPIO_8 3 IO
MSS_MIBSPIA_HOSTIRQ 5 O
MSS_MIBSPIB_CS2 6 IO
MSS_GPIO_2 7 IO
MSS_GPIO_8 10 IO
B16 PAD_DA MSS_UARTA_RX MSS_GPIO_12 0 IO Output Disabled Pull Up
MSS_CPTS0_TS_SYNC 1 O
MSS_GPIO_8 3 IO
MSS_UARTB_TX 4 IO
MSS_UARTA_RX 5 IO
DSS_UARTA_TX 6 IO
C16 PAD_DB MSS_UARTA_TX SOP[4] During Power-up I Output Disabled
MSS_GPIO_13 0 IO
MSS_CPTS0_HW2TSPUSH 1 I
MSS_GPIO_9 3 IO
MSS_UARTB_RX 4 IO
MSS_UARTA_TX 5 IO
DSS_UARTA_RX 6 IO
A15 PAD_DC DSS_UARTA_TX MSS_GPIO_14 0 IO Output Disabled Pull Up
MSS_CPTS0_HW1TSPUSH 1 I
MSS_GPIO_10 3 IO
DSS_UARTA_TX 4 IO
MSS_UARTA_RX 6 IO
B14 PAD_DD DSS_UARTA_RX MSS_GPIO_15 0 IO Output Disabled Pull Up
DSS_UARTA_RX 1 IO
MSS_GPIO_11 3 IO
MSS_UARTA_TX 6 IO
A14 PAD_DE MSS_UARTB_TX SOP[3] During Power-up I Output Disabled
MSS_GPIO_0 0 IO
DSS_UARTA_TX 1 IO
MSS_EPWMB_SYNCI 3 I
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
LVDS_VALID 8 O
MSS_GPIO_31 12 IO
B13 PAD_DF XREF_CLK0 MSS_GPIO_1 0 IO Output Disabled Pull Down
XREF_CLK0 1 I
MSS_GPIO_8 3 IO
MCU_CLKOUT 6 O
MSS_GPIO_30 12 IO
D11 PAD_DG XREF_CLK1 MSS_GPIO_2 0 IO Output Disabled Pull Down
XREF_CLK1 1 I
MSS_GPIO_9 3 IO
PMIC_CLKOUT 7 O
MSS_GPIO_29 12 IO
(1) BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
(2) BALL NAME: Mechanical name from package device (name is taken based on an example implementation).
(3) SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
(4) MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
(5) TYPE: Signal type and direction:
  • I = Input
  • O = Output
  • IO = Input or Output
(6) BALL RESET STATE: The state of the terminal at power-on reset
(7) PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  • Pull Up: Internal pullup
  • Pull Down: Internal pulldown
  • HiZ
(8) Pin Mux Control Value maps to lower 4 bits of register.
(9) There are some PADs that are not mapped to dedicated BGA PINs. These unused PADs need to be disabled in application.