JAJSNB2D November   2021  – September 2024 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configurations and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions - Digital
    4. 5.4 Signal Descriptions - Analog
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.5.2 Hardware Requirements
      3. 6.5.3 Impact to Your Hardware Warranty
    6. 6.6  Power Supply Specifications
    7. 6.7  Power Consumption Summary
    8. 6.8  RF Specifications
    9. 6.9  Thermal Resistance Characteristics
    10. 6.10 Power Supply Sequencing and Reset Timing
    11. 6.11 Input Clocks and Oscillators
      1. 6.11.1 Clock Specifications
    12. 6.12 Peripheral Information
      1. 6.12.1  QSPI Flash Memory Peripheral
        1. 6.12.1.1 QSPI Timing Conditions
        2. 6.12.1.2 QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 6.12.1.3 QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
      2. 6.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.12.2.1 MibSPI Peripheral Description
        2. 6.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 6.12.2.2.1 SPI Timing Conditions
          2. 6.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
          3. 6.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
        3. 6.12.2.3 SPI Peripheral Mode I/O Timings
          1. 6.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
      3. 6.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 6.12.3.1  RGMII Timing Conditions
        2. 6.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 6.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 6.12.3.4  RGMII Receive Clock Timing Requirements
        5. 6.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 6.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 6.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 6.12.3.8  RMII Receive Clock Timing Requirements
        9. 6.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 6.12.3.10 MII Transmit Switching Characteristics
        11. 6.12.3.11 MII Receive Clock Timing Requirements
        12. 6.12.3.12 MII Receive Timing Requirements
        13. 6.12.3.13 MII Transmit Clock Timing Requirements
        14. 6.12.3.14 MDIO Interface Timings
      4. 6.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 6.12.4.1 LVDS Interface Configuration
        2. 6.12.4.2 LVDS Interface Timings
      5. 6.12.5  UART Peripheral
        1. 6.12.5.1 SCI Timing Requirements
      6. 6.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 6.12.6.1 I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
      7. 6.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 6.12.8  CSI2 Receiver Peripheral
        1. 6.12.8.1 CSI2 Switching Characteristics
      9. 6.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 6.12.10 General-Purpose Input/Output
        1. 6.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
    13. 6.13 Emulation and Debug
      1. 6.13.1 Emulation and Debug Description
      2. 6.13.2 JTAG Interface
        1. 6.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 6.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 6.13.3 ETM Trace Interface
        1. 6.13.3.1 ETM TRACE Timing Requirements
        2. 6.13.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 RF Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interfaces
    4. 7.4 Other Subsystems
      1. 7.4.1 Hardware Accelerator Subsystem
      2. 7.4.2 Security – Hardware Security Module
      3. 7.4.3 ADC Channels (Service) for User Application
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Short and Medium Range Radar
    3. 9.3 Reference Schematic
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 Device Support
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation support
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 ドキュメントの更新通知を受け取る方法
    8. 10.8 静電気放電に関する注意事項
    9. 10.9 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.4 Signal Descriptions - Analog

INTERFACESIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.
TransmittersTX1OSingle ended transmitter 1 O/PB3
TX2OSingle ended transmitter 2 O/PB5
TX3OSingle ended transmitter 3 O/PB7
TX4(1)OSingle ended transmitter 4 O/PB9
ReceiversRX1ISingle ended receiver 1 I/PM2
RX2ISingle ended receiver 2 I/PK2
RX3ISingle ended receiver 3 I/PH2
RX4ISingle ended receiver 4 I/PF2
ResetNRESETIPower on reset for chip. Active lowH16
Reference OscillatorCLKPIIn XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port		D1
CLKMIIn XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground		B1
Reference clockOSC_CLKOUTOReference clock output from clocking subsystem after cleanup PLLA11
Bandgap voltageVBGAPODevice's Band Gap Reference OutputK4
Power supplyVDDPower1.2V digital power supplyE12,E13,E14,F14,H14,J14,K14,L14,N6,N14,P6,P7,P9,P10,P11,P13,P14
VDD_SRAMPower1.2V power rail for internal SRAMV7
VNWAPower1.2V power rail for SRAM array back biasV13
VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supplyA13,B18,R18,V8,V15
VIOIN_18Power1.8V supply for CMOS IOD18,U18,V10
VDDA_18CLKPower1.8V supply for clock moduleD9
VDDA_18PMPower1.8V supply for PM moduleR1
VIOIN_18LVDSPower1.8V supply for LVDS portK17
VIOIN_18CSIPower1.8V supply for CSI portK18
VPPPowerVoltage supply for fuse chainU3
Power supplyVIDDA_10RF1Power1V Analog and RF supply,VDDA_10RF1 and VDDA_10RF2 could be shorted on the boardM4
VDDA_10RF2Power1V Analog and RF supplyD6, D7
VDDA_18BBPower1.8V Analog base band power supplyP1
VDDA_18VCOPower1.8V RF VCO supplyE4
VSS(3)GroundDigital groundA12,A18,E11,E18,F8,F9,F10,F11,F12,F13,G7,G8,G9,G10,G11,G12,G13,G14,H7,H8,H9,H10,H11,H12,H13,J7,J8,J9,J10,J11,J12,J13,K7,K8,K9,K10,K11,K12,K13,K16,L7,L8,L9,L10,L11,L12,L13,M7,M8,M9,M10,M11,M12,M13,M14,N7,N8,N9,N10,N11,N12,N13,P8,P12,P18,V2,V9,V14,V18
VSSA(4)GroundAnalog groundA1,A2,A4,A6,A8,A10,B2,B4,B6,B8,B10,B11,C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,D2,D3,E1,E2,E3,F3,F6,F7,G1,G2,G3,G6,H3,H6,J1,J2,J3,J6,K3,K6,L1,L2,L3,L6,M3,M6,N1,N2,N3,V1
Internal LDO output/inputsVOUT_14APLLOInternal LDO outputH4
VOUT_14SYNTHOInternal LDO outputG4
General purpose ADC inputs for external voltage monitoring(2)ADC1IOADC Channel 1P3
ADC2IOADC Channel 2P2
ADC3IOADC Channel 3R3
ADC4IOADC Channel 4R2
ADC5IOADC Channel 5T3
ADC6IOADC Channel 6U2
ADC7IOADC Channel 7T1
ADC8IOADC Channel 8T2
ADC9IOADC Channel 9U1
(1) TX4 is only applicable in the AWR294x variant with 4 transmitters i.e. AWR2944.
(2) For details, see Section 7.4.3
(3) Corner BGAs are VSS and redundant, meaning if they fail the device will still function.
(4) The VSSA BGAs around the launches are not redundant and are required for functionality.