JAJSNK9A December   2021  – December 2022 OPT4001

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Spectral Matching to Human Eye
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Output Register CRC and Counter
        1. 8.3.3.1 Output Sample Counter
        2. 8.3.3.2 Output CRC
      4. 8.3.4 Output Register FIFO
      5. 8.3.5 Threshold Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 Interrupt Modes of Operation
      3. 8.4.3 Light Range Selection
      4. 8.4.4 Selecting Conversion Time
      5. 8.4.5 Light Measurement in Lux
      6. 8.4.6 Light Resolution
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing and Reading
        1. 8.5.2.1 High-Speed I2C Mode
        2. 8.5.2.2 Burst Read Mode
        3. 8.5.2.3 General-Call Reset Command
        4. 8.5.2.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 ALL Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Electrical Interface
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Optical Interface
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Optomechanical Design (PicoStar Variant)
          2. 9.2.1.2.2 Optomechanical Design (SOT-5X3 Variant)
        3. 9.2.1.3 Application Curves (PicoStar Variant)
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Soldering and Handling Recommendations (SOT-5X3 Variant)
        2. 9.5.2.2 Soldering and Handling Recommendations (PicoStar Variant)
          1. 9.5.2.2.1 Solder Paste
          2. 9.5.2.2.2 Package Placement
          3. 9.5.2.2.3 Reflow Profile
          4. 9.5.2.2.4 Special Flexible Printed-Circuit Board (FPCB) Recommendations
          5. 9.5.2.2.5 Rework Process
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

8.6.1 ALL Register Map

8.6.1.1 Register 0h (offset = 0h) [reset = 0h]

Figure 8-11 Register 0h
15 14 13 12 11 10 9 8
EXPONENT RESULT_MSB
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-12 Register 00 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT R 0h EXPONENT output. Determines the full-scale range of the light measurement. Used as a scaling factor for lux calculation
11-0 RESULT_MSB R 0h Result register MSB (Most significant bits). Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

8.6.1.2 Register 1h (offset = 1h) [reset = 0h]

Figure 8-13 Register 1h
15 14 13 12 11 10 9 8
RESULT_LSB
R-0h
7 6 5 4 3 2 1 0
COUNTER CRC
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-14 Register 01 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB R 0h Result register LSB(Least significant bits). Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4 COUNTER R 0h Sample counter. Rolling counter which increments for every conversion
3-0 CRC R 0h CRC bits.
R[19:0]=MANTISSA=((RESULT_MSB<<8)+ RESULT_LSB
X[0]=XOR(E[3:0],R[19:0],C[3:0]) XOR of all bits
X[1]=XOR(C[1],C[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(C[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

8.6.1.3 Register 2h (offset = 2h) [reset = 0h]

Figure 8-15 Register 2h
15 14 13 12 11 10 9 8
EXPONENT_FIFO0 RESULT_MSB_FIFO0
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_FIFO0
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-16 Register 02 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_FIFO0 R 0h EXPONENT register from FIFO 0
11-0 RESULT_MSB_FIFO0 R 0h RESULT_MSB Register from FIFO 0

8.6.1.4 Register 3h (offset = 3h) [reset = 0h]

Figure 8-17 Register 3h
15 14 13 12 11 10 9 8
RESULT_LSB_FIFO0
R-0h
7 6 5 4 3 2 1 0
COUNTER_FIFO0 CRC_FIFO0
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-18 Register 03 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_FIFO0 R 0h RESULT_LSB Register from FIFO 0
7-4 COUNTER_FIFO0 R 0h COUNTER Register from FIFO 0
3-0 CRC_FIFO0 R 0h CRC Register from FIFO 0

8.6.1.5 Register 4h (offset = 4h) [reset = 0h]

Figure 8-19 Register 4h
15 14 13 12 11 10 9 8
EXPONENT_FIFO1 RESULT_MSB_FIFO1
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_FIFO1
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-20 Register 04 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_FIFO1 R 0h EXPONENT register from FIFO 1
11-0 RESULT_MSB_FIFO1 R 0h RESULT_MSB Register from FIFO 1

8.6.1.6 Register 5h (offset = 5h) [reset = 0h]

Figure 8-21 Register 5h
15 14 13 12 11 10 9 8
RESULT_LSB_FIFO1
R-0h
7 6 5 4 3 2 1 0
COUNTER_FIFO1 CRC_FIFO1
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-22 Register 05 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_FIFO1 R 0h RESULT_LSB Register from FIFO 1
7-4 COUNTER_FIFO1 R 0h COUNTER Register from FIFO 1
3-0 CRC_FIFO1 R 0h CRC Register from FIFO 1

8.6.1.7 Register 6h (offset = 6h) [reset = 0h]

Figure 8-23 Register 6h
15 14 13 12 11 10 9 8
EXPONENT_FIFO2 RESULT_MSB_FIFO2
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_FIFO2
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-24 Register 06 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_FIFO2 R 0h EXPONENT register from FIFO 2
11-0 RESULT_MSB_FIFO2 R 0h RESULT_MSB Register from FIFO 2

8.6.1.8 Register 7h (offset = 7h) [reset = 0h]

Figure 8-25 Register 7h
15 14 13 12 11 10 9 8
RESULT_LSB_FIFO2
R-0h
7 6 5 4 3 2 1 0
COUNTER_FIFO2 CRC_FIFO2
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-26 Register 07 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_FIFO2 R 0h RESULT_LSB Register from FIFO 2
7-4 COUNTER_FIFO2 R 0h COUNTER Register from FIFO 2
3-0 CRC_FIFO2 R 0h CRC Register from FIFO 2

8.6.1.9 Register 8h (offset = 8h) [reset = 0h]

Figure 8-27 Register 8h
15 14 13 12 11 10 9 8
THRESHOLD_L_EXPONENT THRESHOLD_L_RESULT
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
THRESHOLD_L_RESULT
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-28 Register 08 Field Descriptions
Bit Field Type Reset Description
15-12 THRESHOLD_L_EXPONENT R/W 0h Threshold low register exponent
11-0 THRESHOLD_L_RESULT R/W 0h Threshold low register result

8.6.1.10 Register 9h (offset = 9h) [reset = BFFFh]

Figure 8-29 Register 9h
15 14 13 12 11 10 9 8
THRESHOLD_H_EXPONENT THRESHOLD_H_RESULT
R/W-Bh R/W-Fh
7 6 5 4 3 2 1 0
THRESHOLD_H_RESULT
R/W-FFh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-30 Register 09 Field Descriptions
Bit Field Type Reset Description
15-12 THRESHOLD_H_EXPONENT R/W Bh Threshold high register exponent
11-0 THRESHOLD_H_RESULT R/W FFFh Threshold high register result

8.6.1.11 Register Ah (offset = Ah) [reset = 3208h]

Figure 8-31 Register Ah
15 14 13 12 11 10 9 8
QWAKE 0 RANGE CONVERSION_TIME
R/W-0h R/W-0h R/W-Ch R/W-2h
7 6 5 4 3 2 1 0
CONVERSION_TIME OPERATING_MODE LATCH INT_POL FAULT_COUNT
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-32 Register 0A Field Descriptions
Bit Field Type Reset Description
15-15 QWAKE R/W 0h Quick Wake-up from Standby in one shot mode by not powering down all circuits. Applicable only in One-shot mode and helps get out of standby mode faster with penalty in power consumption compared to full standby mode.
14-14 0 R/W 0h Must read or write 0
13-10 RANGE R/W Ch Controls the full-scale light level range of the device. The format of this register is same as the EXPONENT register for all values from 0 to 8. PicoStar™ variant:
0 : 328lux
1 : 655lux
2 : 1.3klux
3 : 2.6klux
4 : 5.2klux
5 : 10.5klux
6 : 21klux
7 : 42klux
8 : 83klux
12 : Auto-Range
SOT-5X3 variant:
0 : 459lux
1 : 918lux
2 : 1.8klux
3 : 3.7klux
4 : 7.3klux
5 : 14.7klux
6 : 29.4klux
7 : 58.7klux
8 : 117.4klux
12 : Auto-range
9-6 CONVERSION_TIME R/W 8h Controls the device conversion time
0 : 600us
1 : 1ms
2 : 1.8ms
3 : 3.4ms
4 : 6.5ms
5 : 12.7ms
6 : 25ms
7 : 50ms
8 : 100ms
9 : 200ms
10 : 400ms
11 : 800ms
5-4 OPERATING_MODE R/W 0h Controls device mode of operation
0 : Power-down
1 : Forced auto-range One-shot
2 : One-shot
3 : Continuous
3-3 LATCH R/W 1h Controls the functionality of the interrupt reporting mechanisms for INT pin for the threshold detection logic.
2-2 INT_POL R/W 0h Controls the polarity or active state of the INT pin.
0 : Active Low
1 : Active High
1-0 FAULT_COUNT R/W 0h Fault count register instructs the device as to how many consecutive fault events are required to trigger the threshold mechanisms: the flag high (FLAG_H) and the flag low (FLAG_L) registers.
0 : One fault Count
1 : Two Fault Counts
2 : Four Fault Counts
3 : Eight Fault Counts

8.6.1.12 Register Bh (offset = Bh) [reset = 8011h]

Figure 8-33 Register Bh
15 14 13 12 11 10 9 8
1 0 0 0 0 0 0 0
R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 INT_DIR INT_CFG 0 I2C_BURST
R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-34 Register 0B Field Descriptions
Bit Field Type Reset Description
15-5 1024 R/W 400h Must read or write 1024
4-4 INT_DIR R/W 1h Determines the direction of the INT pin.
0 : Input
1 : Output
3-2 INT_CFG R/W 0h Controls the output interrupt mechanism after end of conversion
0 : SMBUS Alert
1 : INT Pin asserted after every conversion
2: Invalid
3: INT pin asserted after every 4 conversions (FIFO full)
1-1 0 R/W 0h Must read or write 0
0-0 I2C_BURST R/W 1h When set, enables I2C burst mode minimizing I2C read cycles by auto incrementing read register pointer by 1 after every register read

8.6.1.13 Register Ch (offset = Ch) [reset = 0h]

Figure 8-35 Register Ch
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 OVERLOAD_FLAG CONVERSION_READY_FLAG FLAG_H FLAG_L
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-36 Register 0C Field Descriptions
Bit Field Type Reset Description
15-4 0 R/W 0h Must read or write 0
3-3 OVERLOAD_FLAG R 0h Indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the full-scale range.
2-2 CONVERSION_READY_FLAG R 0h Conversion ready flag indicates when a conversion completes. The flag is set to 1 at the end of a conversion and is cleared (set to 0) when register address 0xC is either read or written with any non-zero value
0 : Conversion in progress
1 : Conversion is complete
1-1 FLAG_H R 0h Flag high register identifies that the result of a conversion is measurement than a specified level of interest. FLAG_H is set to 1 when the result is larger than the level in the THRESHOLD_H_EXPONENT and THRESHOLD_H_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.
0-0 FLAG_L R 0h Flag low register identifies that the result of a measurement is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the THRESHOLD_LOW_EXPONENT and THRESHOLD_L_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.

8.6.1.14 Register 11h (offset = 11h) [reset = 121h]

Figure 8-37 Register 11h
15 14 13 12 11 10 9 8
0 0 DIDL DIDH
R/W-0h R/W-0h R-0h R-1h
7 6 5 4 3 2 1 0
DIDH
R-21h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-38 Register 11 Field Descriptions
Bit Field Type Reset Description
15-14 0 R/W 0h Must read or write 0
13-12 DIDL R 0h Device ID L
11-0 DIDH R 121h Device ID H