JAJSNR9B April   2016  – April 2022 INA301-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Alert Output ( ALERT Pin)
      2. 7.3.2 Current-Limit Threshold
        1. 7.3.2.1 Resistor-Controlled Current Limit
          1. 7.3.2.1.1 Resistor-Controlled, Current-Limit Example
        2. 7.3.2.2 Voltage-Source-Controlled Current Limit
      3. 7.3.3 Hysteresis
    4. 7.4 Device Functional Modes
      1. 7.4.1 Alert Mode
        1. 7.4.1.1 Transparent Output Mode
        2. 7.4.1.2 Latch Output Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting a Current-Sensing Resistor
        1. 8.1.1.1 Selecting a Current-Sensing Resistor Example
      2. 8.1.2 Input Filtering
      3. 8.1.3 INA301-Q1 Operation With Common-Mode Voltage Transients Greater Than 36 V
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4.1.2 Latch Output Mode

Some applications do not have the functionality available to continuously monitor the state of the output ALERT pin to detect an overcurrent condition as described in the Section 7.4.1.1 section. A typical example of this application is a system that is only able to poll the ALERT pin state periodically to determine if the system is functioning correctly. If the device is set to transparent mode in this type of application, the state change of the ALERT pin might be missed when ALERT is pulled low to indicate an out-of-range event, if the out-of-range condition does not appear during one of these periodic polling events. Latch mode is specifically intended to accommodate these applications.

The INA301-Q1 is placed into the corresponding output modes based on the signal connected to RESET (see Table 7-4). The difference between latch mode and transparent mode is how the ALERT pin responds when an overcurrent event ends. In transparent mode (RESET = low), when the differential input signal drops below the limit threshold level after the ALERT pin asserts because of an overcurrent event, the ALERT pin state returns to the default high setting to indicate that the overcurrent event has ended.

Table 7-4 Output Mode Settings
OUTPUT MODERESET PIN SETTING
Transparent modeRESET = low
Latch modeRESET = high

In latch mode (RESET = high), when an overlimit condition is detected and the ALERT pin is pulled low, the ALERT pin does not return to the default high state when the differential input signal drops below the alert threshold level. In order to clear the alert, pull the RESET pin low for at least 100 ns. Pulling the RESET pin low allows the ALERT pin to return to the default high level, provided that the differential input signal has dropped below the alert threshold. If the input signal is still greater than the threshold limit when the RESET pin is pulled low, the ALERT pin remains low. When the alert condition is detected by the system controller, the RESET pin can be set back to high in order to place the device back in latch mode.

The latch and transparent modes represented in Figure 7-3 show that when VIN drops back below the VLIMIT threshold for the first time, the RESET pin is pulled high. With the RESET pin is pulled high, the device is set to latch mode, so that the ALERT pin output state does not return high when the input signal drops below the VLIMIT threshold. Only when the RESET pin is pulled low does the ALERT pin return to the default high level, thus indicating that the input signal is below the limit threshold. When the input signal drops below the limit threshold for the second time, the RESET pin is already pulled low. The device is set to transparent mode at this point and the ALERT pin is pulled back high as soon as the input signal drops below the alert threshold.

GUID-CC39960F-39A2-4A06-ABE2-4C7DA087F88F-low.gifFigure 7-3 Transparent Mode vs. Latch Mode