JAJSOA3B February   2023  – June 2024 TPS25948

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Active Current Limiting
        3. 7.3.3.3 Short-Circuit Protection
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Reverse Current Protection
      6. 7.3.6 Overtemperature Protection (OTP)
      7. 7.3.7 Fault Response and Indication (FLT)
      8. 7.3.8 Supply Good Indication (SPLYGD/SPLYGD)
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Setting Overvoltage Threshold
        2. 8.3.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.3.2.3 Setting Overcurrent Threshold (ILIM)
        4. 8.3.2.4 Setting Overcurrent Blanking Interval (tITIMER)
      3. 8.3.3 Application Curves
    4. 8.4 Active ORing
    5. 8.5 Priority Power MUXing
    6. 8.6 Parallel Operation
    7. 8.7 USB PD Port Protection
    8. 8.8 Power Supply Recommendations
      1. 8.8.1 Transient Protection
      2. 8.8.2 Output Short-Circuit Measurements
    9. 8.9 Layout
      1. 8.9.1 Layout Guidelines
      2. 8.9.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Priority Power MUXing

Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment require preference of one source to another. For example, mains power (wall-adapter) has the priority over the internal battery back-up power. These applications demand for switchover from mains power to backup power only when main input voltage falls below a user defined threshold. The TPS25948xx devices provide a simple solution for priority power multiplexing needs.

Figure 8-14 shows a typical priority power multiplexing implementation using TPS259480x devices. When primary (priority) power source (IN1) is present and within the valid range (not in UV/OV condition), the primary path device path powers the OUT bus irrespective of whether auxiliary supply voltage (VIN2) is greater than, equal to or less than primary supply voltage (VIN1). The device in auxiliary path is held in off condition by forcing its OVLO pin to high using the SPLYGD signal from the primary path device.

Once the primary supply voltage falls outside the user-defined valid operating range (UV/OV condition), the primary path device de-asserts the SPLYGD which signals the auxiliary path device to turn on and the system starts operating from the auxiliary supply. During this transition, the auxiliary path device bypasses its dVdt limited startup and performs a fast recovery to start delivering power within tSWOV.

When the primary supply is restored, the primary path device turns on fully at a defined slew rate and then asserts its SPLYGD pin high to turn the auxiliary path device off, allowing a seamless transition from auxiliary to the primary supply with minimal output voltage droop and with no shoot-through current.

A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the switchover from one supply to another. This in turn depends on multiple factors including the output load current (ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).

While switching from primary supply (VIN1) to auxiliary supply (VIN2), the minimum bus voltage can be calculated using Equation 15. Here, the switchover time (tSW) is equal to the fast OVLO recovery time (tSWOV) taken by the TPS259480x variants to turn on fully and start delivering current to the load.

Equation 15. VOUT,min (V) = min (VIN1, VIN2) - tSW (µs) × ILOAD (A)COUT (µF)

While switching from auxiliary supply (VIN2) to primary supply (VIN1), the minimum bus voltage can be calculated using Equation 16. Here the maximum switchover time is equal to the RCB recovery time (tSWRCB), depending on whether VIN1 is equal to or lower than VIN2 to start with.

Equation 16. VOUT,min (V) = min (VIN1, VIN2) - VFWDTH (V) - tSWRCB (µs) × ILOAD (A)COUT (µF)

The SPLYGD pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and delivering power to the load.

TPS25948 Priority Power MUXing With 2 × TPS259480x - Option 1Figure 8-14 Priority Power MUXing With 2 × TPS259480x - Option 1

This configuration provides the most compact priority power MUXing solution with multiple benefits, including active current limit protection on both channels as well as overvoltage protection on primary channel. It also provides the fastest switchover time from primary to auxiliary, but at the cost of a slightly increased quiescent current on the auxiliary path while primary path is active. Also, it uses the fewest external components, but at the cost of bypassing overvoltage protection on auxiliary channel.

The following waveforms illustrate the TPS259480x performance in a priority power MUXing configuration.

TPS25948 TPS259480x Power MUX - Switchover Between Primary and Auxiliary SuppliesFigure 8-15 TPS259480x Power MUX - Switchover Between Primary and Auxiliary Supplies
TPS25948 TPS259480x Power MUX - Switchover Between Primary and Auxiliary SuppliesFigure 8-16 TPS259480x Power MUX - Switchover Between Primary and Auxiliary Supplies

ere is a possible variation to the above configuration in case overvoltage protection is needed on both channels. This needs an additional signal N-FET to drive the OVLO pin of the auxiliary path device as shown in Figure 8-17. The switchover times are similar to the previous configuration.

TPS25948 Priority Power MUXing With 2 × TPS259480x - Option 2Figure 8-17 Priority Power MUXing With 2 × TPS259480x - Option 2

Another variation of the previous configuration ensures minimum quiescent current on the auxiliary channel while primary channel is active, but at the cost of additional N-FET to drive the EN/UVLO pin of auxiliary path device as shown in Figure 8-18. At the same time, it has a higher switchover delay from primary to auxiliary supply as compared to the previous configuration.

TPS25948 Priority Power MUXing With 2 × TPS259480x - Option 3Figure 8-18 Priority Power MUXing With 2 × TPS259480x - Option 3

While switching from a higher supply rail to lower supply rail, the minimum bus voltage can be calculated using Equation 17. Here, the switchover time is equal to the time taken by the device to come out of reverse current blocking state (tSWRCB).

Equation 17. VOUT,min (V) = min (VIN1, VIN2) - VFWDTH (V) - tSWRCB (µs) × ILOAD (A)COUT (µF)

While switching from a lower supply rail to higher supply rail, the minimum bus voltage can be calculated using Equation 18. Here, the switchover time (tSW) is the time taken by the device to turn on fully and start delivering current to the load, which is equal to the device turn-on time (tON), which in turn includes the turn-on delay (tD,ON) and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.

Equation 18. VOUT,min (V) = min (VIN1, VIN2) - tSW (µs) × ILOAD (A)COUT (µF)
Note:
  1. Power MUXing can be done either between two similar rails (such as 12-V Primary and 12-V Aux, 3.3-V Primary and 3.3-V Aux) or between dissimilar rails (such as 12-V Primary and 5-V Aux or vice versa).
  2. For power MUXing cases with skewed voltage combinations, care must be taken to design circuit components on EN/OVLO pins for the lower voltage channel devices such that the absolute maximum ratings on those pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Recommended Operating Conditions table for more details.