JAJSOA3B February   2023  – June 2024 TPS25948

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Active Current Limiting
        3. 7.3.3.3 Short-Circuit Protection
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Reverse Current Protection
      6. 7.3.6 Overtemperature Protection (OTP)
      7. 7.3.7 Fault Response and Indication (FLT)
      8. 7.3.8 Supply Good Indication (SPLYGD/SPLYGD)
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Setting Overvoltage Threshold
        2. 8.3.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.3.2.3 Setting Overcurrent Threshold (ILIM)
        4. 8.3.2.4 Setting Overcurrent Blanking Interval (tITIMER)
      3. 8.3.3 Application Curves
    4. 8.4 Active ORing
    5. 8.5 Priority Power MUXing
    6. 8.6 Parallel Operation
    7. 8.7 USB PD Port Protection
    8. 8.8 Power Supply Recommendations
      1. 8.8.1 Transient Protection
      2. 8.8.2 Output Short-Circuit Measurements
    9. 8.9 Layout
      1. 8.9.1 Layout Guidelines
      2. 8.9.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Reverse Current Protection

The TPS25948xx functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme (linear ORing control) enables graceful turn off of the MOSFET during a reverse current event and ensures there's almost no DC reverse current flow.

The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast response (tRCB) to transient reverse currents. Once the device enters reverse current blocking condition, it waits for the (VIN – VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap (FRS).

TPS25948 Reverse Current Blocking ResponseFigure 7-11 Reverse Current Blocking Response

The following waveforms illustrate the reverse current blocking performance in various scenarios.

During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism ensures minimum jump or glitch on the input rail.

TPS25948 Reverse Current Blocking Performance During Fast Voltage Step at OutputFigure 7-12 Reverse Current Blocking Performance During Fast Voltage Step at Output

During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there is almost no DC current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.

TPS25948 Reverse Current Blocking Performance During Slow Voltage Ramp at OutputFigure 7-13 Reverse Current Blocking Performance During Slow Voltage Ramp at Output

When the input supply droops or gets disconnected while the output storage element (bulk capacitor or super capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN. This ensures maximum holdup time for the output storage element in critical power back-up applications.

It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the supply is connected.

TPS25948 Reverse Current Blocking Performance During Input Supply FailureFigure 7-14 Reverse Current Blocking Performance During Input Supply Failure

The TPS259481x/2x variants provide the option of disabling the reverse current blocking scheme using the RCBCTRL pin. Leaving the RCBCTRL pin floating or pulling it high enables the reverse current blocking during steady-state, while pulling the pin low disables it.

Note: RCBCTRL pin controls the reverse current blocking mechanism only during steady-state. It has no effect during disabled or fault state where the reverse current blocking is always active.