JAJSP62G December   2002  – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Driver Electrical Characteristics
    6. 8.6  Receiver Electrical Characteristics
    7. 8.7  Driver Switching Characteristics
    8. 8.8  Receiver Switching Characteristics
    9. 8.9  Receiver Equalization Characteristics
    10. 8.10 Power Dissipation
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Test Mode Driver Disable
      2. 10.4.2 Equivalent Input and Output Schematic Diagrams
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Noise Considerations for Equalized Receivers
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

11.2.3 Application Curves

Figure 11-2 illustrates the benefits of integrated receiver equalization as implemented in the SN65HVD23 transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel 2 (bottom) shows the output of the receiver.

Figure 11-3 illustrates the benefits of integrated receiver equalization as implemented in the SN65HVD24 transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel 3 (bottom) shows the output of the receiver.

GUID-531E2DDD-A145-45BD-B1B4-335A834833FB-low.gifFigure 11-2 SN65HVD23 Receiver Performance at 25 Mbps Over 150 Meter Cable
GUID-7574DF3A-F550-4314-BA42-EAFDE9619CD0-low.gifFigure 11-3 SN65HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable