JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.9 PWM/PFM and Reset (MODE/RESET)

This pin can be configured as an alternative MODE pin (in case MODE/STBY is configured for STBY-function) or as a RESET pin. The configuration of the pin is selected by MODE_RESET_CONFIG in MFP_2_CONFIG register. The polarity of this pin can be configured by writing to MODE_RESET_POLARITY in MFP_1_CONFIG register. The polarity-configuration must not change after power-up. Only MODE/RESET or MODE/STBY must be configured as MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is ignored.

MODE/RESET configured as 'MODE':

  • If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters. This selection is only applicable in quasi-fixed-frequency mode.
  • Forcing this pin for longer than tDEGLITCH_MFP forces the buck-regulators into PWM-mode (irrespective of load current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be configured as 'MODE'.
  • The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in MFP_1_CONFIG register.
  • A change of the MODE does not cause a state-transition.
  • During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect after the ramp completed.

MODE/RESET configured as 'RESET':

  • In RESET configuration, this pin is edge sensitive, but still applies the deglitch time. Consequently, toggling this pin and holding the pin for longer than tDEGLITCH_RESET causes a reset.
  • By default, RESET is deasserted and RESET requests, via pin or I2C, are only serviced if the device is in ACTIVE state, STBY state, or transitions between these 2 states.
  • The TPS6522005-EP supports WARM or COLD reset. The configuration is made by bit WARM_COLD_RESET_CONFIG in MFP_2_CONFIG register.
    • If configured for COLD reset, the device executes the power down sequence and transitions to INITIALIZE state. Then, EEPROM is reloaded and rails power-up again in normal power-up-sequence, provided there are no faults and no OFF-request. The execution of a COLD-reset sets the bit COLD_RESET_ISSUED in POWER_UP_STATUS_REG register. The read-out of this bit allows to track if a COLD-reset was performed. The bit gets set regardless if the reset was commanded by I2C or by the pin. The nINT-pin does not toggle based on this bit. Write W1C to clear the bit.
    • If configured for WARM reset, all enabled rails remain on, but the output voltage of rails that support dynamic voltage change is reset to the boot-voltage. Specifically, following configurations get reset to their boot-value: BUCK1_VSET, BUCK2_VSET, BUCK3_VSET, LDO1_VSET, LDO2_VSET, LDO1_BYP_CONFIG, LDO2_BYP_CONFIG and VSEL_SD_I2C_CTRL.

      All other bits, even in the same register, remain at their current state. For example, LDOx_LSW_CONFIG, BUCKx_BW_SEL, BUCKx_UV_THR_SEL and the MFP_1_CONFIG register bits do NOT get reset during a WARM-reset.

      WARM Reset cannot override the VSEL_SD-pin command. In other words: even if a WARM Reset occurs, if the VSEL_SD pin is commanding 1.8V-LDO mode, that remain in effect.

  • A reset can also be triggered by writing to the bit WARM_RESET_I2C_CTRL respectively the bit COLD_RESET_I2C_CTRL in MFP_CTRL register.

Note: Shut-down-faults and OFF-requests take priority over a RESET-request. If a RESET-requests occurs simultaneously with one of those, the device enters INITIALIZE state and requires a new ON-request to start up.

Reset requests, via pin or I2c, are only serviced in ACTIVE state, STBY state, or a transition between these two states.

Please see below truth-table for pin- and I2C-commands.

Table 6-4 MODE/RESET configuration

Pin Name

Pin Configuration

(MODE_RESET_CONFIG)

Pin Polarity

(MODE_RESET_POLARIT Y)

Pin state

(schematic)

I2C control

(MODE_I2C_CTRL)

Resulting Function

MODE/RESET

MODE*

x

x

1h

forced PWM

MODE/RESET

MODE*

0h

L

0h

auto-PFM

MODE/RESET

MODE*

0h

H

0h

forced PWM

MODE/RESET

MODE*

1h

L

0h

forced PWM

MODE/RESET

MODE*

1h

H

0h

auto-PFM

MODE/RESET

RESET

0

L

x

RESET

MODE/RESET

RESET

0

H

x

normal operation

MODE/RESET

RESET

1

L

x

normal operation

MODE/RESET

RESET

1

H

x

RESET

The * for MODE indicates that the MODE/RESET pin takes priority in case both, MODE/RESET and MODE/STBY are configured as 'MODE', and thus the respective pin to be observed is MODE/RESET.