JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS6522005-EP RHB Package, 32-pin QFN (Top View)Figure 4-1 RHB Package, 32-pin QFN (Top View)
Table 4-1 Pin Functions
PIN NAME PIN NO. TYPE DESCRIPTION CONNECTION if not used (output rails must be permanently disabled)
FB_B1 1 I Feedback Input for Buck1. Connect to Buck1 output filter. Nominal output voltage is configured in EEPROM. Connect to GND
LX_B1_1 2 PWR Switch Pin for Buck1. Connect one side of the Buck1-inductor to this pin. Leave floating
LX_B1_2 3 PWR 2nd Switch Pin for Buck1. Connect one side of the Buck1-inductor to this pin. Connect to LX_B1_1. Leave floating
PVIN_B1_1 4 PWR Power Input for BUCK1. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B1_1 pin must not exceed voltage on VSYS pin. Connect to VSYS
PVIN_B1_2 5 PWR 2nd Power Input for BUCK1. This pin shares the bypass capacitor from pin 4. Voltage on PVIN_B1_2 pin must not exceed voltage on VSYS pin. Connect to VSYS
PVIN_LDO1 6 PWR Power Input for LDO1. Voltage on PVIN_LDO1 pin must not exceed voltage on VSYS pin. Connect to VSYS
VLDO1 7 PWR Output Voltage of LDO1. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. Leave floating
GPO1 8 O General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail. Leave floating
SDA 9 I/O Data Pin for the I2C Serial Port. The I2C logic levels depend on the external pull-up voltage. Connect to VIO
SCL 10 I Clock Pin for the I2C Serial Port. The I2C logic levels depend on the external pull-up voltage. Connect to VIO
nINT 11 O Interrupt Request Output. Open-drain driver is pulled low for fault conditions. Released if bit is cleared Leave floating
VSEL_SD/ VSEL_DDR 12 I Multi-Function-Pin:

Configured as VSEL_SD: SD-card-IO-voltage select. Connected to SoC. Trigger a voltage change between 1.8 V and register-based VOUT on LDO1 or LDO2. Polarity is configurable.

Configured as VSEL_DDR: DDR-voltage selection. Hard-wired pull-up (1.35 V), pull-down (register based VOUT) or floating (1.2 V)

 n/a (connect to GND)
VSYS 13

PWR

 Input supply pin for reference system. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor (can be shared with PVIN-capacitors). n/a
VDD1P8 14 PWR Internal Reference Voltage: For Internal Use Only. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. n/a
AGND 15 GND Ground pin for Analog GND n/a
GPIO 16 I/O

GPO-configuration: General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail.

GPIO-configuration:

Synchronizing I/O. Used to synchronize two or more TPS6522005-EP. The pin is level-sensitive.

 Leave floating
GPO2 17 O General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail. Leave floating
nRSTOUT 18 O Reset-output to SoC. Controlled by sequencer. High in ACTIVE and STBY state. Leave floating
VLDO2 19 PWR Output Voltage of LDO2. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. Leave floating
PVIN_LDO2 20 PWR Power Input for LDO2. Bypass this pin to ground with a 2.2 μF or greater ceramic capacitor. Voltage on PVIN_LDO2 pin must not exceed voltage on VSYS pin. Connect to VSYS
VLDO3 21 PWR Output Voltage of LDO3. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. Leave floating
PVIN_LDO34 22 PWR Power Input for LDO3 and LDO4. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_LDO34 pin must not exceed voltage on VSYS pin. Connect to VSYS
VLDO4 23 PWR Output Voltage of LDO4. Nominal output voltage is configured in EEPROM.Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. Leave floating
FB_B3 24 I Feedback Input for Buck3. Connect to Buck3 output filter. Nominal output voltage is configured in EEPROM. Connect to GND
EN/PB/VSENSE 25 I ON-request input.

Configured as EN: Device enable pin, high level is ON-request, low-level is OFF-request.

Configured as PB: Push-button monitor input. 600 ms low-level is an ON-request, 8 s low-level is an OFF-request.

Configured as VSENSE: Power-fail comparator input. Set sense voltage using a resistor divider connected from the input to the pre-regulator to this pin to ground. Detects rising/falling voltage on pre-regulator and triggers ON- / OFF-request.

The pin is edge-sensitive with a wait-time in PB-configuration and deglitch time for EN- and VSENSE-configuration.

 n/a (configure as EN and connect to VSYS)
PVIN_B3 26 PWR Power Input for BUCK3. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B3 pin must not exceed voltage on VSYS pin. Connect to VSYS
LX_B3 27 PWR Switch Pin for Buck3. Connect one side of the Buck3-inductor to this pin. Leave floating
MODE/RESET 28 I Multi-Function-Pin:

Configured as MODE: Connected to SoC or hard-wired pull-up/-down. Forces the Buck-converters into PWM or permits auto-entry in PFM-mode.

Configured as RESET: Connected to SoC. Forces a WARM or COLD reset (configurable), WARM reset resetting output voltages to defaults, COLD reset sequencing down all enabled rails and power up again.

Polarity is configurable.

The pin is level-sensitive for MODE-configuration, edge-sensitive for RESET-configuration.

 n/a (tie high or low, dependent on configuration, see 'PWM/PFM and Reset (MODE/RESET)'
LX_B2 29 PWR Switch Pin for Buck2. Connect one side of the Buck2-inductor to this pin. Leave floating
PVIN_B2 30 PWR Power Input for BUCK2. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B2 pin must not exceed voltage on VSYS pin. Connect to VSYS
MODE/STBY 31 I Multi-Function-Pin:

Configured as MODE:

Connected to SoC or hard-wired pull-up/-down. Forces the Buck-converters into PWM or permits auto-entry in PFM-mode.

Configured as STBY: Low-power-mode command, disables selected rails.

Both functions, MODE and STBY, can be combined.

The pin is level-sensitive.

 n/a (tie high or low, dependent on configuration, see 'PWM/PFM and Low Power Modes (MODE/STBY)'
FB_B2 32 I Feedback Input for Buck2. Connect to Buck2 output filter. Nominal output voltage is configured in EEPROM. Connect to GND
PGND PowerPad GND Power-Ground. The exposed pad must be connected to a continuous ground plane of the printed circuit board by multiple interconnect vias directly under the TPS6522005-EP to maximize electrical and thermal conduction. n/a