During power-up, the output of the nINT pin does depend on whether any INT_SOURCE flags are set and the configuration of the MASK_EFFECT bit in INT_MASK_BUCKS register-. If one or more flags are set, then nINT pin is pulled low and is only released high after those flags have been cleared by writing ‘1’ to them. Note, the nINT-pin can only transition 'high' if a VIO-voltage for the pull-up is available.

In ACTIVE or STBY state, the nINT pin signals any event or fault condition to the host processor. Whenever a fault or event occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is driven low. In case the device transitions to INITIALIZE state, the nINT pin is pulled low as well, regardless if the transition is triggered by an OFF-request or a fault.

If the fault is no longer present, a W1C (write '1' to clear) needs to be performed on the failure bits. This command also allows the nINT-pin to release (return to Hi-Z state).

If a failure persists, the corresponding bit remains set and the INT pin remains low.

The UV-faults can be individually masked per rail in INT_MASK_UV registers. The thermal sensors can individually be masked by SENSOR_x_WARM_MASK in the MASK_CONFIG register. The effect of the masking for UV and WARM is defined globally by MASK_EFFECT bits in MASK_CONFIG register.

The nINT reaction for RV-faults is defined globally by MASK_INT_FOR_RV bits in MASK_CONFIG register.

• 00b = no state change, no nINT reaction, no bit set
• 01b = no state change, no nINT reaction, bit set
• 10b = no state change, nINT reaction, bit set (same as 11b)
• 11b = no state change, nINT reaction, bit set (same as 10b)