The GPIO (pin#16) is an input/output digital pin, however, the input-functionality is only used in multi-PMIC configuration. This pin behaves as GPO (general purpose output) when configured for single PMIC and behaves as GPIO (general purpose input-output) when configured for multi-device. This configuration can be made on register field MULTI_DEVICE_ENABLE (address 0x1F). When configured for "multi-device", GPIO allows to synchronize the power-up and power-down sequence of multiple TPS6522005-EP devices for applications requiring additional rails. The GPIO pin is used to indicate the status of each PMIC so they are always in the same state and same sequence slot. At the beginning of each sequence slot, all the TPS6522005-EP PMICs drive GPIO pin low. After the sequence slot duration finishes, and all rails for that slot have reached the UV threshold, device releases the GPIO pin. Once both devices release the GPIO high, they advance to the next sequence slot together. Since both PMICs are always in the same power-up or power-down slot, multiple rails from each PMIC can be assigned to the same sequence slot. Figure 6-12 shows an example PDN of two TPS6522005-EP devices sharing the same input supply (VSYS), EN pin and GPIO for multi-PMIC operation.

Requirements when synchronizing multiple TPS6522005-EP PMICs

• The GPIO from each PMIC must be tied together, sharing the same pull-up resistor. The pull-up resistance needs to be chosen to meet the maximum allowable rise-time t_{RISE_GPIO} in combination with the capacitance on the GPIO-line to allow for synchronization.
• The EN/PB/VSENSE pin must be tied together sharing the same external ON request. This pin must have the same configuration (same pin config, deglitch, FSD).
• All the TPS6522005-EP PMICs must share the same VSYS supply.
• Each of the TPS6522005-EP PMICs must have a different I2C address if they are connected to the same I2C bus. The I2C address for the second PMIC can be changed on register field I2C_ADDRESS. Once the address is changed, the new value must be stored permanently into the NVM. Refer to NVM Programming for programming instructions.

Figure 6-13 shows the synchronization between two PMICs in Initialize state, before the power-up sequence is executed. While in INITIALIZE state, before the ON request is received, devices hold GPIO low. GPIO is only released when the ON request is received. The external signal driving the ON request must be connected to EN/PB/VSENSE pin of both devices. The PMICs proceed to execute the power-up sequence once both devices are in INITIALIZE state and both devices have received the ON request. This technique ensures both devices start the power-up sequence at the same time, even if they have different internal boot-up times.

Figure 6-14 shows the synchronization between two PMICs during the power-up sequence. An open-drain GPIO is connected between both PMICs, and used as an indicator that the sequence slot has finished for the device. At the beginning of each sequence slot, both PMICs pull down this GPIO. After the device slot timer has expired, and all rails for that slot have reach UV threshold, the GPIO is released high. The combined GPIO goes high when both PMICs have released the GPIO. Once both devices release the GPIO high, both PMICs advance to the next sequence slot. Both PMICs are always in the same sequence slot at the same time.

Figure 6-15 shows the synchronization between two PMICs when transitioning from Active to Standby. In active or standby, GPIO default state is high. When a device wants to change states, it sets the GPIO low for a specific low duration. The low duration determines the type of request. For STANDBY/ACTIVE request, GPIO is set low approximately 38-52us and for OFF request approximately 180-243us. Times are chosen such that devices always see the same state transition, accounting for clock variation and requests happening right after each other. While GPIO is low, devices are counting the time it is low. On GPIO rising edge, devices start the state transition based on low duration. If GPIO stays low longer than the timeout duration, it indicates a GPIO fault and devices transition to INITIALIZE state.

Figure 6-16 shows the synchronization between two PMICs during power-down sequence. Power-down sequence works similarly. If active discharge is enabled for a rail, the sequence slot is extended until rail is discharged below SCG threshold, unless the slot timeout occurs or register field BYPASS_RAILS_DISCHA RGED_CHECK is set. If discharge is disabled for all rails in current slot, the actual slot time is only based on selected slot duration. Once the slot duration expires and rails with active discharge are discharged, devices release the GPIO high. Once all devices release GPIO high, they advance to the next power-down step.

Figure 6-17 shows the timeout synchronization between two PMICs. In case of a fault on an output rail, GPIO is not released. After a timeout, device goes to “timeout synchronization” state, and wait for 3ms before setting GPIO high. Once the combined GPIO goes high, both devices start the power-down sequence. For example: If BUCK1 from PMIC A is shorted to GND, after the slot duration expires, the regulator does not have hit UV and GPIO is not released. If Slot#1 duration is 10ms and PMIC A is 10% fast, it only takes 9ms to timeout. After timeout, device goes to timeout-sync state, at which point GPIO is set high after 3ms. PMIC B rails ramp up properly, but a high state on GPIO from PMIC A is initially not detected due to the fault on BUCK1. PMIC B also goes to timeout-sync state and sets GPIO high after 3ms. After the timeout sync of PMIC B, the combined GPIO is high and both PMICs start power-down together.