JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.3 Push Button and Enable Input (EN/PB/VSENSE)

The EN/PB/VSENSE pin is used to enable the PMIC. The pin can be configured in three ways:

  • Device enable (EN):
    • This pin needs to be pulled high to enable the device. Pulling this pin low disables the device.
    • The deglitch-time of the EN-pin is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
    • The power-up sequence starts if the EN input is above the VIL-threshold low for the configured tDEGL_EN_Rise.
    • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
    • The power-down sequence starts if the EN input is below the VIH-threshold for tDEGL_EN_Fall.
    • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the VIH-threshold. (EN considered level-sensitive)
    • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the VIH-threshold. (EN considered level-sensitive)
  • Push-Button (PB):
    • The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a momentary switch to ground and an external pullup resistor.
    • The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
    • The power-up sequence starts if the PB input is below the VIL-threshold low for the configured tPB_ON.
    • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
    • The PB pin has a rising-edge deglitch tPB_RISE_DEGL to filter bouncing of the switch
    • The power-down sequence starts if the PB input is held low for tPB_OFF-time (not configurable).
    • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
    • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
    • A push-button press is only recognized after VSYS is above VSYS_POR-threshold or the PB must be held long enough after VSYS is above VSYS_POR-threshold.
    • Following bits in the signify the PB-press events:
      • PB_FALLING_EDGE_DETECTED: PB was pressed for a time-interval longer than tPB_INT_DEGL since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
      • PB_RISING_EDGE_DETECTED: PB was released for a time-interval longer than tPB_INT_DEGL since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
      • PB_REAL_TIME_STATUS: Deglitched (tPB_INT_DEGL) real-time status of PB pin. Valid only when EN/PB/VSENSE pin is configured as PB. This bit does not assert the nINT pin.
  • Power-fail comparator input (VSENSE):
    • Connected to a resistor divider from the supply-line of the pre-regulator, this pin can be used to sense the supply-voltage to the pre-regulator.
    • The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
    • Power-up is gated by VSYS being above the VSYSPOR_Rising-threshold and the VSENSE input is above the VVSENSE-threshold (not deglitched)
    • The power-up sequence starts if the VSENSE input rises above VVSENSE.
    • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
    • The power-down sequence starts if the VSENSE input falls below the VVSENSE-threshold for tDEGL_VSENSE_Fall, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.
    • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the VVSENSE-threshold.
    • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the VVSENSE-threshold.
  • OFF-request by I2C-command
    • An OFF-request can also be triggered by an I2C-command to I2C_OFF_REQ in MFP_CTRL register.
    • After an OFF-request, a new ON-request is required:
      • In case of EN-configuration, the EN input requires a rising edge (EN considered edge-sensitive)
      • In case of PB-configuration, the PB needs to be pressed for a valid ON-request
      • In case of VSENSE-configuration, the VSENSE input requires a rising edge (VSENSE considered edge-sensitive). This ON request can be triggered by power cycling the pre-regulator.
      • The falling-edge deglitch time for EN or VSENSE configuration tDEGL_EN/VSENSE_I2C is shorter than the deglitch-time for pin-induced OFF-requests (tDEGL_EN_Fall and tDEGL_VSENSE_Fall). The deglitch-times for PB-configuration remain.
  • First Supply detection (FSD)
    • First Supply detection (FSD) allows power-up as soon as supply voltage is applied, even if EN/PB/VSENSE pin is at OFF_REQ status.
    • FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE.
    • FSD can be enabled by setting PU_ON_FSD bit in MFP_2_CONFIG.
    • At first power-up the EN/PB/VSENSE pin is treated as if the pin had a valid ON request.
    • Once VSYS is above the VSYSPOR_Rising-threshold, the PMIC
      • loads the EEPROM
      • enters INITIALIZE state
      • perform the discharge-check
      • initiates the power-up-sequence, regardless of the EN/PB/VSENSE-pin-state.
    • To signify the power-up based on FSD, the device sets bit POWER_UP_FROM_FSD in POWER_UP_STATUS_REG register. The nINT-pin does not toggle based on this bit. Write W1C to clear the bit.
    • Thereafter, the EN/PB/VSENSE-pin is treated as if the pin had a valid ON-request, until we enter ACTIVE state (at the expiration of the last slot in the power-up-sequence).
    • After that the device adheres to post-deglitch EN/PB/VSENSE-pin-status: if pin status has changed prior to entering ACTIVE state or in ACTIVE state, the device does adhere to the pin state. For example, if the EN/PB/VSENSE-pin is configured for EN, the device does power down in case the EN-pin is low (for longer than the deglitch time) at the time the device enters ACTIVE state.
    • The duration for how long the ON-request is considered valid, regardless of the pin-state, can be controlled by length of nRSTOUT slot (and empty slots thereafter), as the PMIC enters ACTIVE state only after the last slot of the sequence expired.