JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
POS MIN NOM MAX UNIT
3.1.1 VVSYS Input voltage 2.5 (1) 5.5 V
3.1.2 VPVIN_B1, VPVIN_B2,
VPVIN_B3
VLX_B1, VLX_B2,
VLX_B3		 BUCKx Pins 2.5 5.5 (2) V
3.1.3 ΔVVSYS_PVIN_Bx Voltage by which VPVIN_Bx may exceed VVSYS  0 mV
3.1.4 ΔVVSYS_PVIN_LDO1,LDO2 Voltage by which VPVIN_LDO1 or VPVIN_LDO2  may exceed VVSYS 0 mV
3.1.5 ΔVVSYS_VLDO34 Voltage by which  VVSYS must exceed LDO output voltage (VLDO3, VLDO4); VVSYS = 2.5V to 3.45V; LDO mode 150 mV
3.1.6 ΔVVSYS_VLDO34 Voltage by which  VVSYS must exceed LDO output voltage (VLDO3, VLDO4); VVSYS = 3.45V to 5.5V in LDO-mode or VVSYS = 2.5V to 5.5V in LSW-mode  n/a mV
3.1.7 CPVIN_B1, CPVIN_B2,
CPVIN_B3		 BUCKx Input Capacitance 3.9 4.7 µF
3.1.8 LB1, LB2, LB3 BUCKx Output Inductance 330 470 611 nH
3.1.9a COUT_B1, COUT_B2,
COUT_B3		 BUCKx Output Capacitance, forced PWM or auto-PFM, low bandwidth case 10 75 µF
3.1.9b COUT_B1, COUT_B2,
COUT_B3		 BUCKx Output Capacitance, fixed frequency, low BW case 12 36 µF
3.1.10a COUT_B1, COUT_B2,
COUT_B3		 BUCKx Output Capacitance, forced PWM or auto-PFM, high bandwidth case 30 220 µF
3.1.10b COUT_B1, COUT_B2,
COUT_B3		 BUCKx Output Capacitance, fixed frequency, high BW case 48 144 µF
3.1.11 VFB_B1, VFB_B2,
VFB_B3		 BUCKx FB Pins 0 5.5 (2) V
3.1.12 VPVIN_LDO1, VPVIN_LDO2 LDO Input Voltage 1.5 5.5 (2) V
3.1.13 VPVIN_LDO1, VPVIN_LDO2 LDO Input Voltage in bypass mode 1.5 3.6 V
3.1.14 VPVIN_LDO1, VPVIN_LDO2 Allowable delta between VPVIN_LDOx and configured VVLDOx in bypass mode -200 200 mV
3.1.15 VVLDO1, VVLDO2 LDO Output Voltage Range 0.6 3.4 V
3.1.16 CPVIN_LDO1, CPVIN_LDO2 LDO Input Capacitance 1.6 2.2 µF
3.1.17 CVLDO1, CVLDO2 LDO Output Capacitance 1.6 2.2 20 µF
3.1.18 VPVIN_LDO3, VPVIN_LDO4 LDO Input Voltage 2.2 5.5 (2) V
3.1.19 VVLDO3, VVLDO4 LDO Output Voltage Range 1.2 3.3 V
3.1.20 CPVIN_LDO34 LDO Input Capacitance 2.2 4.7 µF
3.1.21 CVLDO3, CVLDO4 LDO Output Capacitance 1.6 2.2 30 (3) µF
3.1.22 VVDD1P8 VDD1P8 pin 0 1.8 V
3.1.23 CVDD1P8 Internal Regulator Decoupling Capacitance 1 2.2 4 µF
3.1.24 CVSYS VSYS Input Decoupling Capacitance 1 2.2 µF
3.1.25 VnINT, VnRSTOUT Digital Outputs 0 3.4 V
3.1.26 VGPO1, VGPO2, VGPIO Digital Outputs 0 5.5 (2) V
3.1.27 VSCL, VSDA I2C Interface 0 3.4 V
3.1.28 VEN/PB/VSENSE, VMODE/STBY,
VMODE/RESET,
VVSEL_SD/VSEL/DDR		 Digital Inputs 0 5.5 (2) V
3.2.1 tVSYS_RAMP_RISE Input voltage rising ramp Time, Input voltage controlled by a pre-regulator.  VVSYS = VPVIN_Bx = VPVIN_LDOx = 0V to 5V
 0.1 600000 ms
3.2.2 tVSYS_RAMP_FALL Input voltage falling Ramp Time, VVSYS = VPVIN_Bx = VPVIN_LDOx = 5V to 2.5V 0.4 600000 ms
3.3.1 TA  Operating free-air temperature –55 125 °C
3.3.2 TJ  Operating junction temperature –55 150 °C
(1) For EEPROM programming, VSYS(min)=3.3V
(2) Must not exceed VSYS
(3) In slow-ramp-mode. Fast-ramp supports 15µF maximum