JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.12 I2C Interface

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3V or 1.8V.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
11.1.1 VOL Low-level Output Voltage VIO = 3.6V, IOL = 3mA for Standard mode and Fast mode, IOL = 20mA for Fast mode+, SDA 0.40 V
11.1.2 VIL Low-level Input Voltage SDA, SCL 0.40 V
11.1.3 VIH High-level Input Voltage SDA, SCL 1.26 V
11.1.4 VHYST Input buffer Hysteresis EN_BP/VSENSE, MODE_RESET, MODE_STBY, SDA, SCL, GPIO 100 500 mV
11.1.5 CB Capacitive Load for SDA and SCL 400 pF
Timing Requirements
11.2.1 ƒSCL Serial Clock Frequency Standard mode 100 kHz
11.2.2 Fast mode 400
11.2.3 Fast mode+ 1 MHz
11.3.1 tLOW SCL low Time Standard mode 4.7 µs
11.3.2 Fast mode 1.3
11.3.3 Fast mode+ 0.50
11.4.1 tHIGH SCL high Time Standard mode 4.0 µs
11.4.2 Fast mode 0.60
11.4.3 Fast mode+ 0.26
11.5.1 tSU;DAT Data setup Time Standard mode 250 ns
11.5.2 Fast mode 100
11.5.3 Fast mode+ 50
11.6.1 tHD;DAT Data hold Time Standard mode 10 3450 ns
11.6.2 Fast mode 10 900
11.6.6 Fast mode+ 10
11.7.1 tSU;STA Setup Time for a Start or a REPEATED Start Condition Standard mode 4.7 µs
11.7.2 Fast mode 0.60
11.7.3 Fast mode+ 0.26
11.8.1 tHD;STA Hold Time for a Start or a REPEATED Start Condition Standard mode 4.7 µs
11.8.2 Fast mode 0.60
11.8.3 Fast mode+ 0.26
11.9.1 tBUF Bus free Time between a STOP and Start Condition Standard mode 4.7 µs
11.9.2 Fast mode 1.3
11.9.3 Fast mode+ 0.50
11.10.1 tSU;STO Setup Time for a STOP Condition Standard mode 0.60 µs
11.10.2 Fast mode 0.60
11.10.3 Fast mode+ 0.26
11.10.1 trDA Rise Time of SDA Signal Standard mode, VIO = 1.8V, RPU = 10 kΩ and CB = 400 pF 1000 ns
11.10.2 Fast mode, VIO = 1.8V, RPU = 1 kΩ and CB = 400 pF 20 300
11.10.3 Fast mode+, VIO = 1.8V, RPU = 330 Ω and CB = 400 pF 120
11.12.1 tfDA Fall Time of SDA Signal Standard mode, VIO = 1.8V, RPU = 10 kΩ and CB = 400 pF 300 ns
11.12.2 Fast mode, VIO = 1.8V, RPU = 1 kΩ and CB = 400 pF 6.5 300
11.12.3 Fast mode+, VIO = 1.8V, RPU = 330 Ω and CB = 400 pF 6.5 120
11.13.1 trCL Rise Time of SCL Signal Standard mode, VIO = 1.8V, RPU = 10 kΩ and CB = 400 pF 1000 ns
11.13.2 Fast mode, VIO = 1.8V, RPU = 1 kΩ and CB = 400 pF 20 300
11.13.3 Fast mode+, VIO = 1.8V, RPU = 330 Ω and CB = 400 pF 120
11.14.1 tfCL Fall Time of SCL Signal Standard mode, VIO = 1.8V, RPU = 10 kΩ and CB = 400 pF 300 ns
11.14.2 Fast mode, VIO = 1.8V, RPU = 1 kΩ and CB = 400 pF 6.5 300
11.14.3 Fast mode+, VIO = 1.8V, RPU = 330 Ω and CB = 400 pF  6.5 120
11.15.1 tSP Pulse Width of Spike suppressed (SCL and SDA Spikes that are less than the indicated Width are suppressed) Fast mode, and fast mode+ 50 ns