JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.8 General Purpose LDOs (LDO1, LDO2)

over operating free-air temperature range (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
7.1.1 VIN_LDO Input Voltage (LDO-mode)(1) LDO-mode, maximum VSYS 1.5 5.5 V
7.1.2 VIN_LDO_BYP Input Voltage (bypass-mode)(1) (5) Bypass-mode, maximum VSYS 1.5 3.4  V
7.1.3 VIN_LDO_LSW Input Voltage (LSW-mode)(1) LSW-mode, maximum VSYS 1.5 5.5 V
7.1.4 VOUT_LDO LDO Output Voltage configurable Range LDO mode, with 50-mV steps, VIN - VOUT > 300 mV 0.6 3.4 V
7.1.5 VOUT_LDO_BYP LDO Output Voltage configurable Range in bypass-mode Bypass mode, configurable VOUT range with 50-mV steps 1.5 3.4 V
7.1.6 VOUT_STEP Output Voltage Steps LDO mode, 0.6V ≤ VOUT ≤ 3.4V 50 mV
7.1.7 VDROPOUT Dropout Voltage VINmin ≤ VIN ≤ VINmax, IOUT = 400 mA 150 300 mV
7.1.10 RBYPASS_H Bypass Resistance, high output voltage 2.5 V ≤ VIN ≤ 3.6 V, VIN ≤ VSYS, IOUT = 400 mA, bypass-mode 200 mΩ
7.1.11 RBYPASS_L Bypass Resistance, low output voltage 1.5 V ≤ VIN ≤ 2.5 V, VIN ≤ VSYS, IOUT = 400 mA, bypass-mode 250 mΩ
7.1.12 RLSW_H LSW Resistance, high output voltage 2.5 V ≤ VIN ≤ 5.5 V, VIN ≤ VSYS, IOUT = 400 mA, LSW-mode 200 mΩ
7.1.13 RLSW_L LSW Resistance, low output voltage 1.5 V ≤ VIN ≤ 2.5 V, VIN ≤ VSYS, IOUT = 400 mA, LSW-mode 250 mΩ
7.2.1 VLOAD_TRANSIENT Transient Load Regulation, ΔVOUT IOUT = 20% to 80% to 20% of IOUT_MAX, tr = tf = 1 µs –35 35 mV
7.2.2 VLINE_TRANSIENT Transient Line Regulation VIN  step = 600 mVPP, tR = tF = 10 µs, LDO not in dropout condition, LDO-mode –25 25 mV
7.2.3 NOISERMS RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 600 μVRMS
7.2.4 VRIPPLE Voltage Ripple 5 mVPP
7.3.1 IOUT_MAX Output Current VPVIN_LDOxmin ≤ VIN ≤ VPVIN_LDOxmax,
Applies to LDO-, bypass- and LSW-mode		 400 mA
7.3.2 ICURRENT_LIMIT Short Circuit Current Limit VIN = 3.6V, VOUT = 0V 600 980 1600 mA
7.3.3 IIN_RUSH_LDO LDO Inrush Current LDO-mode, with maximum 20-µF load connected to VLDOx, , IOUT = 0 mA or 400mA 1500 mA
7.3.4 IIN_RUSH_LDO_BYP LDO Inrush Current in bypass-mode Bypass-mode, with maximum 50-µF load connected to VLDOx 1500 mA
7.3.5 IIN_RUSH_LDO_LSW LDO Inrush Current in LSW-mode LSW-mode, with maximum 50-µF load connected to VLDOx 1500 mA
7.3.6 RDISCHARGE Pulldown Discharge Resistance at LDO Output Active only when converter is disabled. Applies to LDO-, bypass- and LSW-mode 100 200 300 Ω
7.3.7a IQ_ACTIVE_LDO Quiescent Current in ACTIVE state at 25°C,
LDO-mode		 LDO-mode, IOUT = 0 mA, 
TJ = 25°C		 50 62 µA
7.3.7b IQ_ACTIVE_LDO Quiescent Current in ACTIVE state -40°C to 125°C,
LDO-mode		 LDO-mode, IOUT = 0 mA, 
TJ = -40°C to 125°C		 50 65 µA
7.3.7b IQ_ACTIVE_LDO
Quiescent Current in ACTIVE state -40°C to 150°C,
LDO-mode
 		 LDO-mode, IOUT = 0 mA, 
TJ = -40°C to 150°C		 50 66 µA
7.3.8a IQ_ACTIVE_LDO_BYP Quiescent Current in ACTIVE state at 25°C,
bypass-mode		 bypass-mode, IOUT = 0 mA, 
TJ = 25°C		 43 48 µA
7.3.8b IQ_ACTIVE_LDO_BYP Quiescent Current in ACTIVE state -40°C to 125°C,
bypass-mode		 bypass-mode, IOUT = 0 mA, 
TJ = -40°C to 125°C		 43 50 µA
7.3.8b IQ_ACTIVE_LDO_BYP
Quiescent Current in ACTIVE state -40°C to 150°C,
bypass-mode
 		 bypass-mode, IOUT = 0 mA, 
TJ = -40°C to 150°C		 43 50 µA
7.3.9a IQ_ACTIVE_LDO_LSW Quiescent Current in ACTIVE state at 25°C,
LSW-mode		 LSW-mode, IOUT = 0 mA, 
TJ = 25°C		 46 53 µA
7.3.9b IQ_ACTIVE_LDO_LSW Quiescent Current in ACTIVE state -40°C to 125°C,
LSW-mode		 LSW-mode, IOUT = 0 mA, 
TJ = -40°C to 125°C		 46 53 µA
7.3.9b IQ_ACTIVE_LDO_LSW
Quiescent Current in ACTIVE state -40°C to 150°C,
LSW-mode
 		 LSW-mode, IOUT = 0 mA, 
TJ = -40°C to 150°C		 46 54 µA
7.4.1 CIN Input Filtering Capacitance (2) Connected from PVIN_LDOx to GND
Applies to LDO-, bypass- and LSW-mode		 1.6 2.2 µF
7.4.2 COUT Output Filtering Capacitance(3) Connected from VLDOx to GND, LDO-mode 1.6 2.2 4 µF
7.4.3 COUT_TOTAL Total Capacitance at Output (Local + POL), LDO-mode(4) 1 MHz < f < 10 MHz 20 µF
7.4.4 COUT_TOTAL_BYP Total Capacitance at Output (Local + POL), bypass-mode(4) 1 MHz < f < 10 MHz 50 µF
7.4.5 COUT_TOTAL_LSW Total Capacitance at Output (Local + POL), LSW-mode(4) 1 MHz < f < 10 MHz 50 µF
7.4.6 CESR Filtering capacitor ESR max 1 MHz < f < 10 MHz 10 20 mΩ
Timing Requirements
7.5.1 tRAMP Ramp Time LDO in LDO- and bypass-mode Measured from enable to 98% of target value, LDO-mode or bypass-mode, measured when enabled individually, assuming no residual voltage 950 µs
7.5.2 tRAMP_SLEW Ramp up Slew Rate in LDO- and bypass-mode VOUT from 0.3 V to 90% of VOUT 12 mV/µs
7.5.3 tRAMP_LSW Ramp Time LSW-mode Measured from enable to target value, LSW-mode, assuming no residual voltage 1250 µs
7.5.4 tRAMP_SLEW Ramp up Slew Rate in LSW-mode VOUT from 0.3 V to 90% of VOUT 12 mV/µs
7.5.5 tTRANS_1P8_3P3 Transition Time 1.8V - 3.3V VIN = 4.0V, IOUT = 300mA 2 ms
7.5.6 tTRANS_3P3_1P8 Transition Time 3.3V - 1.8V VIN = 4.0V, IOUT = 300mA 2 ms
(1) PVIN_LDOx must not exceed VSYS
(2) Input capacitors must be placed as close as possible to the device pins.
(3) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.
(4) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable
(5) PVIN_LDOx voltage must be within (configured VOUT) and (configured VOUT + 200mV), maximum 3.6V.