JAJSP72
August 2024
TPSM83102
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Rating
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Undervoltage Lockout (UVLO)
7.3.2
Enable and Soft Start
7.3.3
Adjustable Output Voltage
7.3.4
Reverse Current Operation
7.3.5
Protection Features
7.3.5.1
Input Overvoltage Protection
7.3.5.2
Short Circuit Protection
7.3.5.3
Thermal Shutdown
7.4
Device Functional Modes
7.5
Programming
7.5.1
Serial Interface Description
7.5.2
Standard-, Fast-, and Fast-Mode Plus Protocol
7.5.3
I2C Update Sequence
7.6
Register Map
7.6.1
Register Description
7.6.1.1
Register Map
7.6.1.2
Register CONTROL1 (Register address: 0x02; Default: 0x08)
7.6.1.3
Register VOUT (Register address: 0x03; Default: 0x5C)
7.6.1.4
Register CONTROL2 (Register address: 0x05; Default: 0x45)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design with WEBENCH Tools
8.2.2.2
Output Capacitor Selection
8.2.2.3
Input Capacitor Selection
8.2.2.4
Setting the Output Voltage
8.2.3
Application Curves
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.1.2
Development Support
10.1.2.1
Custom Design with WEBENCH Tools
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
12.2
Mechanical Data
7.3
Feature Description