JAJSPO4 October   2024 AMC0311D-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information (D Package)
    5. 6.5  Thermal Information (DWV Package)
    6. 6.6  Power Ratings
    7. 6.7  Insulation Specifications (Basic Isolation)
    8. 6.8  Insulation Specifications (Reinforced Isolation)
    9. 6.9  Safety-Related Certifications (Basic Isolation)
    10. 6.10 Safety-Related Certifications (Reinforced Isolation)
    11. 6.11 Safety Limiting Values (D Package)
    12. 6.12 Safety Limiting Values (DWV Package)
    13. 6.13 Electrical Characteristics
    14. 6.14 Switching Characteristics
    15. 6.15 Timing Diagram
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Best Design Practices
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

6.7 Insulation Specifications (Basic Isolation)

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 4 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 4 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 15.4 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage At AC voltage 1130 VPK
VIOWM Maximum-rated isolation
working voltage		 At AC voltage (sine wave) 800 VRMS
At DC voltage 1130 VDC
VIOTM Maximum transient
isolation voltage		 VTEST = VIOTM, t = 60s (qualification test),
VTEST = 1.2 × VIOTM, t = 1s (100% production test)		 4250 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 5000 VPK
VIOSM Maximum surge
isolation voltage(4)		 Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1 		10000 VPK
qpd Apparent charge(5) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s		 ≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s		 ≤ 5
Method b2, at routine test (100% production)(7),
Vpd(ini) = VIOTM = Vpd(m), tini = tm = 1s		 ≤ 5
CIO Barrier capacitance,
input to output(6)		 VIO = 0.5 VPP at 1MHz ~1.5 pF
RIO Insulation resistance,
input to output(6)		 VIO = 500V at TA = 25°C > 1012 Ω
VIO = 500V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification test),
VTEST = 1.2 × VISO, t = 1s (100% production test)		 3000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Maintain the creepage and clearance distance of a board design to make sure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.