JAJSPO4 October 2024 AMC0311D-Q1
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
CIN | Input capacitance | TBD | pF | |||
RINP | Input impedance | INP pin, TA = 25℃ | 1 | GΩ | ||
IIB, INP | Input bias current | INP pin, INP = GND1, TA = 25℃ | –15 | 3.5 | 15 | nA |
CMTI | Common-mode transient immunity | 50 | V/ns | |||
ANALOG OUTPUT | ||||||
Nominal gain | 1 | V/V | ||||
VCMout | Output common-mode voltage | 1.39 | 1.44 | 1.49 | V | |
VCLIPout | Clipping differential output voltage | VOUT = (VOUTP – VOUTN); VIN > VClipping |
2.49 | V | ||
VFAILSAFE | Fail-safe differential output voltage | VDD1 undervoltage, or VDD1 missing | –2.6 | –2.5 | V | |
ROUT | Output resistance | OUTP or OUTN | <0.2 | Ω | ||
Output short-circuit current | On OUTP or OUTN, sourcing or sinking, INP = GND1, outputs shorted to either GND2 or VDD2 |
11 | mA | |||
DC ACCURACY | ||||||
VOS | Input offset voltage(1)(2) | TA = 25°C | –1.5 | ±0.2 | 1.5 | mV |
TCVOS | Input offset thermal drift(1)(2)(4) | –10 | ±3 | 10 | µV/°C | |
EG | Gain error(1) | TA = 25℃ | –0.25% | ±0.05% | 0.25% | |
TCEG | Gain error drift(1)(5) | –40 | ±5 | 40 | ppm/°C | |
Nonlineartity(1) | –0.05% | ±0.01% | 0.05% | |||
Output noise | INP = GND1, BW = 50kHz | TBD | µVrms | |||
PSRR | Power-supply rejection ratio(2) | VDD1 DC PSRR, INP = GND1, VDD1from 3V to 5.5V |
–80 | dB | ||
VDD1AC PSRR, INP = GND1, VDD1with 10kHz / 100mV ripple |
–80 | |||||
VDD2 DC PSRR, INP = GND1, VDD2 from 3V to 5.5V |
–100 | |||||
VDD2 AC PSRR, INP = GND1, VDD2 with 10kHz / 100mV ripple |
–80 | |||||
AC ACCURACY | ||||||
BW | Output bandwidth | 90 | 110 | kHz | ||
THD | Total harmonic distortion(3) | VINP = 2VPP, VINP > 0V, fIN = 10kHz |
–83 | dB | ||
SNR | Signal-to-noise ratio | VINP = 2VPP, fINP = 1kHz, BW = 10kHz | 76 | 79 | dB | |
VINP = 2VPP, fINP = 10kHz, BW = 50kHz | 70 | |||||
POWER SUPPLY | ||||||
IDD1 | High-side supply current | 4.2 | 6.0 | mA | ||
IDD2 | Low-side supply current | 6.0 | 9.9 | mA | ||
VDD1UV | High-side undervoltage detection threshold | VDD1 rising | 2.5 | 2.6 | 2.7 | V |
VDD1 falling | 1.9 | 2.0 | 2.1 | |||
VDD2UV | Low-side undervoltage detection threshold | VDD2 rising | 2.5 | 2.6 | 2.7 | V |
VDD2 falling | 1.9 | 2.0 | 2.1 |