JAJSPU7A June   2024  – September 2024 LMR36503E-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD (Automotive) Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Start-Up, and Shutdown
      2. 7.3.2  External CLK SYNC (with MODE/SYNC)
        1. 7.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/BIAS Input
      6. 7.3.6  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Soft Start and Recovery from Dropout
        1. 7.3.8.1 Recovery from Dropout
      9. 7.3.9  Current Limit and Short Circuit
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 High Temperature Specifications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
          1. 8.2.2.3.1 FB for Adjustable Output
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  CBOOT
        8. 8.2.2.8  VCC
        9. 8.2.2.9  CFF Selection
          1. 8.2.2.9.1 External UVLO
        10. 8.2.2.10 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +175°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24V.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN_R Minimum operating input voltage (rising) Rising threshold 3.4 3.6 V
VIN_F Minimum operating input voltage (falling) Once operating; Falling threshold 2.45 3.0 V
ISD_13p5 Shutdown quiescent current; measured at VIN pin(2) VEN = 0; VIN = 13.5V 0.5 1.1 µA
ISD_24p0 Shutdown quiescent current; measured at VIN pin (2) (5) VEN = 0; VIN = 24V 1 1.6 µA
IQ_13p5_Fixed Non-switching input current; measured at VIN pin(2) VIN = VEN = 13.5V ; VOUT/BIAS = 5.25V, VMODE/SYNC = VRT = 0V; Fixed output 0.25 0.672 1.1 µA
IQ_13p5_Adj Non-switching input current; measured at VIN pin(2) VIN = VEN = 13.5V ; VFB = 1.05V, VMODE/SYNC = VRT = 0V; Adjustable output 10 17 27 µA
IQ_24p0_Fixed Non-switching input current; measured at VIN pin(2) VIN = VEN = 24V ; VOUT/BIAS = 5.25V, VMODE/SYNC = VRT = 0V; Fixed output 0.8 1.2 1.7 µA
IQ_24p0_Adj Non-switching input current; measured at VIN pin(2) VIN = VEN = 24V ; VFB = 1.05V, VMODE/SYNC = VRT = 0V; Adjustable output 10 18 27
µA
IB_13p5 Current into VOUT/BIAS pin (not switching)(2) VIN = 13.5V, VOUT/BIAS = 5.25V, VMODE/SYNC = VRT = 0V; Fixed output 14 17 22 µA
IB_24p0 Current into VOUT/BIAS pin (not switching)(2) VIN = 24V, VOUT/BIAS = 5.25V, VMODE/SYNC = VRT = 0V; Fixed output 14 18 22 µA
ENABLE (EN PIN)
VEN-WAKE Enable wake-up threshold 0.4 V
VEN-VOUT Precision enable high level for VOUT 1.16 1.263 1.36 V
VEN-HYST Enable threshold hysteresis below VEN-VOUT 0.3 0.35 0.4 V
ILKG-EN Enable input leakage current VEN = 3.3V 0.3 8 nA
INTERNAL LDO
VCC Internal VCC voltage Adjustable or fixed  output;  Auto mode 3 3.15 3.25 V
ICC Bias regulator current limit 65 240 mA
VCC-UVLO Internal VCC undervoltage lockout VCC rising under voltage threshold 3 3.3 3.65 V
VCC-UVLO-HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC-UVLO 0.4 0.8 1.2 V
CURRENT LIMITS
IPEAK-MIN Minimum peak inductor current(3) PFM Operation,  Duty Factor = 0 0.067 0.09 0.14 A
IZC Zero cross current(3) Auto mode 0 0.01 0.025 A
IL-NEG Sink current limit (negative)(3) FPWM mode -0.6 -0.72 -0.8 A
POWER GOOD
PG-OV PGOOD upper threshold - rising % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 106 107 110 %
PG-UV PGOOD lower threshold - falling % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 93 94 96.5 %
PG-HYS PGOOD hysteresis - rising/falling  % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 0.85 1.8 2.3 %
VPG-VALID Minimum input voltage for proper PG function 0.75 1 2 V
RPG-EN5p0 RDS(ON) PGOOD output VEN = 5.0V, 1mA pullup current 20 40 85 Ω
RPG-EN0 RDS(ON) PGOOD output VEN = 0 V, 1mA pullup current 10 18 40 Ω
OSCILLATOR (MODE/SYNC)
VMODE_H Sync input and mode high level threshold 1.8 V
VSYNC-HYS Sync input hysteresis 210 300 400 mV
VMODE_L Sync input and mode low level threshold 0.8 V
MOSFETS
RDS-ON-HS High-side MOSFET on-resistance Load = 0.3A 560 1200 mΩ
RDS-ON-LS Low-side MOSFET on-resistance Load = 0.3A 280 550 mΩ
VCBOOT-UVLO Cboot - SW UVLO threshold(4) 2.14 2.3 2.42 V
THERMAL SHUTDOWN
VOLTAGE REFERENCE
VREF Internal reference voltage VIN = 3.6V to 65V, FPWM mode 0.985 1 1.01 V
IFB FB input current Adjustable output, FB = 1V 85 110 nA
SOFT START
tSS Time from first SW pulse to VFB at 90%, of VREF VIN ≥ 3.6V 1.95 2.58 3.2 ms
POWER GOOD
tRESET_FILTER Glitch filter time constant for PG function 15 25 40 µs
tPGOOD_ACT Delay time to PG high signal 1.7 1.956 2.16 ms
OSCILLATOR (MODE/SYNC)
tPULSE_H High duration needed to be recognized as a pulse 100 ns
tPULSE_L Low duration needed to be recognized as a pulse 100 ns
tSYNC High/low signal duration in a valid synchronization signal 6 9 13 µs
tMODE Time at one level needed to indicate FPWM or Auto Mode 18 µs
PWM LIMITS (SW)
tON-MIN Minimum switch on-time IOUT = 0.3A 35 60 97 ns
tOFF-MIN Minimum switch off-time 40 58 80 ns
tON-MAX Maximum switch on-time HS timeout in dropout 7.6 9 9.8 µs
OSCILLATOR (RT)
fOSC_2p2MHz Internal oscillator frequency RT = GND 2.1 2.2 2.3 MHz
fOSC_1p0MHz Internal oscillator frequency RT = VCC 0.93 1 1.05 MHz
fFIXED_400kHz RT = 39.2kΩ 0.3 0.4 0.46 MHz
SPREAD SPECTRUM
(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They can differ from those found in a closed loop application.
(4) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor.
(5) Expected spec change due to 175ºC TJ operation. Based on 175ºC sims from LMR36502.