JAJSPW0B June 2023 – June 2024 TPS543B25T
PRODUCTION DATA
The TPS543B25T can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See Section 6.3.5.2.
Although there is no internal circuit to detect the higher 20% range of the clock frequency, the clock frequency falls outside the stability range of the LC design so the customer is required to make sure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor.