JAJSPW0B June   2023  – June 2024 TPS543B25T

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Internal Linear Regulator and Bypassing
      3. 6.3.3  Enable and Adjustable UVLO
        1. 6.3.3.1 Internal Sequence of Events During Start-Up
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Remote Sense Amplifier and Adjusting the Output Voltage
      7. 6.3.7  Loop Compensation Guidelines
        1. 6.3.7.1 Output Filter Inductor Tradeoffs
        2. 6.3.7.2 Ramp Capacitor Selection
        3. 6.3.7.3 Output Capacitor Selection
        4. 6.3.7.4 Design Method for Good Transient Response
      8. 6.3.8  Soft Start and Prebiased Output Start-Up
      9. 6.3.9  MSEL Pin
      10. 6.3.10 Power Good (PG)
      11. 6.3.11 Output Overload Protection
        1. 6.3.11.1 Positive Inductor Current Protection
        2. 6.3.11.2 Negative Inductor Current Protection
      12. 6.3.12 Output Overvoltage and Undervoltage Protection
      13. 6.3.13 Overtemperature Protection
      14. 6.3.14 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2  Switching Frequency
          3. 7.2.1.2.3  Output Inductor Selection
          4. 7.2.1.2.4  Output Capacitor
          5. 7.2.1.2.5  Input Capacitor
          6. 7.2.1.2.6  Adjustable Undervoltage Lockout
          7. 7.2.1.2.7  Output Voltage Resistors Selection
          8. 7.2.1.2.8  Bootstrap Capacitor Selection
          9. 7.2.1.2.9  VDRV and VCC Capacitor Selection
          10. 7.2.1.2.10 PGOOD Pullup Resistor
          11. 7.2.1.2.11 Current Limit Selection
          12. 7.2.1.2.12 Soft-Start Time Selection
          13. 7.2.1.2.13 Ramp Selection and Control Loop Stability
          14. 7.2.1.2.14 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
IQ(VIN) VIN operating non-switching supply current VEN = 1.3V, VFB = 550mV, VVIN = 12V, 1MHz 1200 1600 µA
ISD(VIN) VIN shutdown supply current VEN = 0V, VVIN = 12V 20 32 µA
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.8 4.00 4.2 V
VINUVLO(H) VIN UVLO hysteresis 150 mV
INTERNAL LDO
VVDRV Internal linear regulator output voltage VVIN = 12V, IVDRV = 25mA 4.5 V
Internal linear regulator dropout voltage VVIN – VVDRV, VVIN = 3.8V, IVDRV = 25mA 390 mV
Internal linear regulator short-circuit current limit VVIN = 12V 150 mA
VCCUVLO(R) VCC UVLO rising threshold 3.4 V
VCCUVLO(H) VCC UVLO hysteresis 0.4 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V
VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V
VEN(H) EN voltage hysteresis 100 mV
EN pin sourcing current VEN = 1.1V 1.75 µA
EN pin sourcing current VEN = 1.3V 11.6 µA
EN HIGH to start of switching delay (1) EN from 0V to 3V rising 1 ms
REFERENCE VOLTAGE
VFB Feedback voltage  TJ = –40°C to 150°C 497.5 500 502.5 mV
IFB(LKG) Input leakage current into FB pin VFB = 500mV, non-switching, VVIN = 12V, VEN = 0V 3 nA
REMOTE SENSE AMPLIFIER
ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA
VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV
SWITCHING FREQUENCY AND OSCILLATOR
fSW Switching frequency RFSEL = 24.3kΩ to AGND  450 500 550 kHz
fSW Switching frequency RFSEL = 17.4kΩ to AGND  675 750 825 kHz
fSW Switching frequency RFSEL = 11.8kΩ to AGND  900 1000 1100 kHz
fSW Switching frequency RFSEL = 8.06kΩ to AGND  1350 1500 1650 kHz
fSW Switching frequency RFSEL = 4.99kΩ to AGND  1980 2200 2420 kHz
SYNCHRONIZATION
VIH(sync) High-level input voltage 1.8 V
VIL(sync) Low-level input voltage 0.8 V
FSYNC(range) Frequency synchronization range to not adversly affect loop stability. (1) FCLK – 20% FCLK + 20%
SOFT-START
tSS1 Soft-start time 0 to 100% VOUT RMSEL = 2.1kΩ 1 ms
tSS2 Soft-start time 0 to 100% VOUT RMSEL = 2.49kΩ 2 ms
tSS3 Soft-start time 0 to 100% VOUT RMSEL = 2.94kΩ 4 ms
tSS4 Soft-start time 0 to 100% VOUT RMSEL = 3.57kΩ 8 ms
POWER STAGE
RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12V, VBOOT-SW = 4.5V 6.5 mΩ
RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VVDRV = 4.5V 2.0 mΩ
VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V
VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V
VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V
TON(min) Minimum ON pulse width 22 28 ns
TOFF(min) Minimum OFF pulse width (1) 115 ns
CURRENT SENSE AND OVERCURRENT PROTECTION
IHS(OC1) High-side peak current limit RMSEL = 2.1kΩ 32.4 36 39.6 A
IHS(OC2) RMSEL = 22.1kΩ 26.1 29 31.9 A
ILS(OC1) Low-side valley current limit RMSEL = 2.1kΩ 26.1 29 31.9 A
ILS(OC2) RMSEL = 22.1kΩ 21.15 23.5 25.85 A
ILS(NOC) Low-side negative current limit Current into SW pin 7 A
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120% VREF
VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80%  VREF
POWER GOOD
Power-Good threshold VFB rising (Good) 88% 91% 94% VREF
Power-Good threshold VFB rising (OV Fault) 112% 115% 118% VREF
Power-Good threshold VFB falling (Good) 103.5% 106.5% 109.5% VREF
Power-Good threshold VFB falling (UV Fault) 79% 82% 85% VREF
IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7V 5 µA
VPG(low) PG low-level output voltage IPG = 2mA, VIN = 12V 0.6 V
Min VIN for valid PG output EN = 0V, PGOOD pulled up to 5V 1 V
PG delay going from low to high 201 us
PG delay going from high to low 11 µs
HICCUP
Hiccup time before re-start 7*tSS ms
OUTPUT DISCHARGE
RDischg Output discharge resistance VVIN = 12V, VSW = 0.5V, power conversion disabled. 100 Ω
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 175 °C
TJ(HYS) Thermal shutdown hysteresis (1) 12 °C
(1) Specified by design