JAJSR89 August 2024 AMC0106M25
ADVANCE INFORMATION
If a full-scale input signal is applied to the AMC0106M25, the device generates a single one or zero every 128 bits at DOUT. Figure 6-5 shows a timing diagram of this process. A single 1 or 0 is generated depending on the actual polarity of the signal being sensed. A full-scale signal is defined when |VIN| ≥ |VClipping|. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.