JAJSRI9B October   2023  – June 2024 LM51772

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck-Boost Control Scheme
        1. 7.3.1.1 Buck Mode
        2. 7.3.1.2 Boost Mode
        3. 7.3.1.3 Buck-Boost Mode
      2. 7.3.2  Power Save Mode
      3. 7.3.3  Programmable Conduction Mode PCM
      4. 7.3.4  Reference System
        1. 7.3.4.1 VIO LDO and nRST-PIN
      5. 7.3.5  Supply Voltage Selection – VSMART Switch and Selection Logic
      6. 7.3.6  Enable and Undervoltage Lockout
        1. 7.3.6.1 UVLO
        2. 7.3.6.2 VDET Comparator
      7. 7.3.7  Internal VCC Regulators
        1. 7.3.7.1 VCC1 Regulator
        2. 7.3.7.2 VCC2 Regulator
      8. 7.3.8  Error Amplifier and Control
        1. 7.3.8.1 Output Voltage Regulation
        2. 7.3.8.2 Output Voltage Feedback
        3. 7.3.8.3 Voltage Regulation Loop
        4. 7.3.8.4 Dynamic Voltage Scaling
      9. 7.3.9  Output Voltage Discharge
      10. 7.3.10 Peak Current Sensor
      11. 7.3.11 Short Circuit - Hiccup Protection
      12. 7.3.12 Current Monitor/Limiter
        1. 7.3.12.1 Overview
        2. 7.3.12.2 Output Current Limitation
        3. 7.3.12.3 Output Current Monitor
      13. 7.3.13 Oscillator Frequency Selection
      14. 7.3.14 Frequency Synchronization
      15. 7.3.15 Output Voltage Tracking
        1. 7.3.15.1 Analog Voltage Tracking
        2. 7.3.15.2 Digital Voltage Tracking
      16. 7.3.16 Slope Compensation
      17. 7.3.17 Configurable Soft Start
      18. 7.3.18 Drive Pin
      19. 7.3.19 Dual Random Spread Spectrum – DRSS
      20. 7.3.20 Gate Driver
      21. 7.3.21 Cable Drop Compensation (CDC)
      22. 7.3.22 CFG-pin and R2D Interface
      23. 7.3.23 Advanced Monitoring Features
        1. 7.3.23.1  Overview
        2. 7.3.23.2  BUSY
        3. 7.3.23.3  OFF
        4. 7.3.23.4  VOUT
        5. 7.3.23.5  IOUT
        6. 7.3.23.6  INPUT
        7. 7.3.23.7  TEMPERATURE
        8. 7.3.23.8  CML
        9. 7.3.23.9  OTHER
        10. 7.3.23.10 ILIM_OP
        11. 7.3.23.11 nFLT/nINT Pin Output
        12. 7.3.23.12 Status Byte
      24. 7.3.24 Protection Features
        1. 7.3.24.1  Thermal Shutdown (TSD)
        2. 7.3.24.2  Over Current Protection
        3. 7.3.24.3  Output Over Voltage Protection 1 (OVP1)
        4. 7.3.24.4  Output Over Voltage Protection 2 (OVP2)
        5. 7.3.24.5  Input Voltage Protection (IVP)
        6. 7.3.24.6  Input Voltage Regulation (IVR)
        7. 7.3.24.7  Power Good
        8. 7.3.24.8  Boot-Strap Under Voltage Protection
        9. 7.3.24.9  Boot-strap Over Voltage Clamp
        10. 7.3.24.10 CRC - CHECK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overview
      2. 7.4.2 Logic State Description
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM51772 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Slope Compensation
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Loop Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Driver Layout
        3. 9.4.1.3 Controller Layout
      2. 9.4.2 Layout Example
    5. 9.5 USB-PD Source with Power Path
    6. 9.6 Parallel (Multiphase) Operation
    7. 9.7 Constant Current LED Driver
    8. 9.8 Wireless Charging Supply
    9. 9.9 Bi-Directional Power Backup
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.2.12 Loop Compensation

This section presents the control loop compensation design procedure for the LM51772 buck-boost controller. The LM51772 operates mainly in buck or boost modes, separated by a transition region, and therefore, the control loop design is done for both buck and boost operating modes. Then, a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically, for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in boost mode.

The boost power stage output pole location is given by:

Equation 57. fp1(boost)= 12π2ROUT× COUT= 995 Hz

where

  • ROUT = 5.0Ω corresponds to the maximum load of 5.0A.

The boost power stage ESR zero location is given by:

Equation 58. fz1= 12π1RESR× COUT= 73.7 kHz

The boost power stage RHP zero location is given by:

Equation 59. fRHP= 12πROUT×(1-DMAX)2L1= 39.1 kHz

where

  • DMAX is the maximum duty cycle at the minimum VIN.

The buck power stage output pole location is given by:

Equation 60. fp1(buck)= 12π1ROUT× COUT=497 Hz

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 59 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design, the crossover frequency must be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 8kHz:

Equation 61. fbw= 8 kHz

For some power stages, the boost RHP zero may not be as restrictive, which happens when the boost maximum duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (fRHP / 3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at three times the buck output pole frequency, which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:

Equation 62. fZC= 1.5 kHz

The compensation gain resistor, Rc1, is calculated with:

Equation 63. RC1= 2π×fbwgmEA×RFB1+RFB2RFB2×ACS×RCS×COUT1-DMAX×11+fbwfRHP2=7.4 kΩ

where

  • DMAX is the maximum duty cycle at the minimum VIN in boost mode.
  • ACS is the current sense amplifier gain: 10.

The compensation capacitor, Cc1, is then calculated from:

Equation 64. CC1= 12π×fZC× Rc1= 14.5nF

The standard values of compensation components are selected to be Rc1 = 7.32kΩ and Cc1 = 15nF.

A high frequency pole (fpc2) is placed using a capacitor (Cc2) in parallel with Rc1 and Cc1. Set the frequency of this pole at seven to ten times of fbw to provide attenuation of switching ripple and noise on COMP while avoiding excessive phase loss at the crossover frequency. For a target fpc2 = 98kHz, Cc2 is calculated using Equation 65:

Equation 65. CC2= 12π×fpc2×Rc1= 263 pF

Select a standard value of 270pF for Cc2. These values provide a good starting point for the compensation design. Each design must be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.